參數(shù)資料
型號： DS3148N
廠商： Maxim Integrated Products
文件頁數(shù)： 53/89頁
文件大?。?/td> 0K
描述： IC 8CH DS3/3 FRAMER 349-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 640mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
57 of 89
Register Name:
HCR2
Register Description:
HDLC Control Register 2
Register Address:
51h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RHWMS2
RHWMS1
RHWMS0
N/A
TLWMS2
TLWMS1
TLWMS0
Default
—
0
—
0
Bits 2 to 0: Transmit Low Watermark Select Bits (TLWMS[2:0]). These control bits determine when the HDLC
controller should set the TLWM status bit in the HSR register. When the transmit FIFO contains less than the
number of bytes specified by these bits, the TLWM status bit is set to logic 1.
TLWMS[2:0]
TRANSMIT LOW WATERMARK (BYTES)
000
16
001
48
010
80
011
112
100
144
101
176
110
208
111
240
Bits 4 to 6: Receive High Watermark Select Bits (RHWMS[2:0]). These control bits determine when the HDLC
controller should set the RHWM status bit in the HSR register. When the receive FIFO contains more than the
number of bytes specified by these bits, the RHWM status bit is set to logic 1.
RHWMS[2:0]
RECEIVE HIGH WATERMARK (BYTES)
000
16
001
48
010
80
011
112
100
144
101
176
110
208
111
240
Register Name:
HSR
Register Description:
HDLC Status Register
Register Address:
54h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RHWM
TLWM
N/A
Default
—
Bit 2: Transmit FIFO Low Watermark (TLWM). This real-time status bit is set to a 1 when the transmit FIFO
contains less than the number of bytes configured by TLWMS[2:0] control bits in the HCR2 register. This bit is
cleared when the FIFO fills beyond the low watermark.
Bit 3: Receive FIFO High Watermark (RHWM). This real-time status bit is set to a 1 when the receive FIFO
contains more than the number of bytes configured by the RHWMS[2:0] control bits in the HCR2 register. This bit is
cleared when the FIFO empties below the high watermark.
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