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參數(shù)資料
| 型號(hào)： | DS2722-F-04 |
| 英文描述： | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
| 中文描述： | 900MHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 463K |
| 代理商： | DS2722-F-04 |
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ML2722
DS2722-F-05
FINAL DATASHEET
DECEMBER 2003
24
Transmit Closed Loop Bit (TXCL): DB4
Used to produce a continuous CW transmitter output for product test with RXON low (see Table 11).
TXCL
TRANSMIT PLL MODE
0
PLL Open Loop, FSK Output
1
PLL Closed Loop, CW Output
Table 11. PLL Mode in Transmit Operation
Transmit Power Control Bit (TPC): DB5
Controls the state of the TPC/TPQ open-drain output (pin 7). Although this bit may be set at any time, the TPC/TPQ pin
only changes state at the falling edge of RXON (see Table 12).
TPC
TPC PIN STATE
0
High Impedance
1
Pulled to Ground
Table 12. TPC Pin State
REGISTER #1, CHANNEL FREQUENCY REGISTER
Channel Frequency Selection Bits (CHQ): <DB11:DB0>
These bits set the channel frequency for the transceiver (see Table 13). With a 6.144MHz or 12.288MHz input to the
REF pin (pin 9), the channel frequency value is calculated by multiplying the CHQ value by 0.512. A 1.024MHz offset is
automatically added in the RECEIVE mode to accommodate the IF frequency. The recommended operating range
value of the CHQ is from 1,024 (400 hex) to 4093 (FFD hex). These bits should be programmed to a valid channel
frequency before XCEN is asserted. The divide ratio is calculated as f
C
/0.512, where f
C
is the channel frequency in
MHz.
B15
B14
B13 TO B2
B1
B0
0
0
PLL divide ratio
0
1
Table 13. Main Divider
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| DS2722-F-05 | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS2722-F-05 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
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| DS2725K | 功能描述:電源管理IC開發(fā)工具 RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
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