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參數(shù)資料
| 型號(hào)： | DS2722-F-04 |
| 英文描述： | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
| 中文描述： | 900MHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 463K |
| 代理商： | DS2722-F-04 |
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ML2722
DS2722-F-05
FINAL DATASHEET
DECEMBER 2003
12
PIN
SIGNAL
NAME
I/O
FUNCTION
DIAGRAM
15
VTUNE
I
VCO Tuning Voltage input from the PLL
loop filter. This pin is very sensitive to
noise coupling and leakage currents.
26
VBG
O
Internal Bandgap Reference Voltage.
Decoupled to ground with a 220nF
capacitor.
28
RSSI/TPI
O
Buffered Analog RSSI output with a
nominal sensitivity of 35mV/dB. An RF
input signal range of –95 to –20 dBm
gives an RSSI voltage output of zero to
2.7 V.
24
VSS
VCC5
100
28
RSSI/TPI
8
TPI
MUX
RSSI
MUX
RSSI
OP
AMP
SERIAL BUS SIGNALS
4
EN
I (CMOS)
Enable pin for the three-wire serial
control bus that sets the operating
frequency and programmable options.
The control registers are loaded on a
low-to-high transition of the signal. Serial
control bus data is ignored when this
signal is high. This is a CMOS input, and
the thresholds are referenced to VDD
and VSS.
5
DATA
I (CMOS)
Serial Control Bus Data. 16-bit words,
which include programming data and the
two-bit address of a control register. This
is a CMOS input, and the thresholds are
referenced to VDD and VSS.
6
CLK
I (CMOS)
Serial control bus data is clocked in on
the rising edge when EN is low. This is a
CMOS input; the thresholds are
referenced to VDD and VSS.
31
VSS
VDD
5.5k
4
EN
8
1.7p
5
DATA
6
CLK
13
VSS
VCC2
3.7k
15
VTUNE
8
1.25V
相關(guān)PDF資料 |
PDF描述 |
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| DS2722-F-05 | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2722-F-05 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
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