
DS26524 Quad T1/E1/J1 Transceiver
3 of 273
8.9.11
8.9.12
8.9.13
8.9.14
8.9.15
8.9.16
8.9.17
8.10
8.10.1
8.10.2
8.11
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.12
8.12.1
8.12.2
9.
9.1
9.1.1
9.1.2
9.1.3
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.3
9.4
9.4.1
9.4.2
9.5
9.6
10.
FUNCTIONAL TIMING ...................................................................................................233
10.1
T1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................233
10.2
T1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................238
10.3
E1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................243
10.4
E1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................245
11.
OPERATING PARAMETERS.........................................................................................248
11.1
T
HERMAL
C
HARACTERISTICS
....................................................................................................249
11.2
L
INE
I
NTERFACE
C
HARACTERISTICS
..........................................................................................249
12.
AC TIMING CHARACTERISTICS..................................................................................250
12.1
M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
........................................................................250
12.2
JTAG I
NTERFACE
T
IMING
.........................................................................................................259
12.3
S
YSTEM
C
LOCK
AC C
HARACTERISTICS
....................................................................................260
13.
JTAG BOUNDARY SCAN AND TEST ACCESS PORT................................................261
13.1
TAP C
ONTROLLER
S
TATE
M
ACHINE
.........................................................................................262
13.1.1
Test-Logic-Reset................................................................................................................................ 262
13.1.2
Run-Test-Idle ..................................................................................................................................... 262
13.1.3
Select-DR-Scan ................................................................................................................................. 262
Transmit Per-Channel Idle Code Insertion........................................................................................... 62
Receive Per-Channel Idle Code Insertion............................................................................................ 62
Per-Channel Loopback ........................................................................................................................ 62
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)................................................................... 62
T1 Programmable In-Band Loop Code Generator............................................................................... 63
T1 Programmable In-Band Loop Code Detection................................................................................ 64
Framer Payload Loopbacks................................................................................................................. 65
HDLC C
ONTROLLERS
................................................................................................................66
Receive HDLC Controller..................................................................................................................... 66
Transmit HDLC Controller.................................................................................................................... 69
L
INE
I
NTERFACE
U
NITS
(LIU
S
)....................................................................................................71
LIU Operation....................................................................................................................................... 74
Transmitter........................................................................................................................................... 75
Receiver............................................................................................................................................... 78
Jitter Attenuator.................................................................................................................................... 81
LIU Loopbacks..................................................................................................................................... 82
B
IT
-E
RROR
-R
ATE
T
EST
(BERT) F
UNCTION
................................................................................84
BERT Repetitive Pattern Set ............................................................................................................... 85
BERT Error Counter............................................................................................................................. 85
DEVICE REGISTERS.......................................................................................................86
R
EGISTER
L
ISTINGS
......................................................................................................................86
Global Register List.............................................................................................................................. 88
Framer Register List............................................................................................................................. 89
LIU and BERT Register List................................................................................................................. 96
R
EGISTER
B
IT
M
APS
......................................................................................................................97
Global Register Bit Map....................................................................................................................... 97
Framer Register Bit Map...................................................................................................................... 98
LIU Register Bit Map.......................................................................................................................... 106
BERT Register Bit Map...................................................................................................................... 106
G
LOBAL
R
EGISTER
D
EFINITIONS
..................................................................................................107
F
RAMER
R
EGISTER
D
EFINITIONS
.................................................................................................122
Receive Register Definitions.............................................................................................................. 122
Transmit Register Definitions............................................................................................................. 181
LIU R
EGISTER
D
EFINITIONS
.........................................................................................................216
BERT R
EGISTER
D
EFINITIONS
.....................................................................................................225