參數(shù)資料
型號(hào): DS26524
廠商: Maxim Integrated Products, Inc.
英文描述: Quad T1/E1/J1 Transceiver
中文描述: 四路T1/E1/J1收發(fā)器
文件頁(yè)數(shù): 22/273頁(yè)
文件大?。?/td> 1212K
代理商: DS26524
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DS26524 Quad T1/E1/J1 Transceiver
22 of 273
NAME
PIN
TYPE
FUNCTION
RCHBLK/
CLK1
E4
RCHBLK/
CLK2
B5
RCHBLK/
CLK3
L6
RCHBLK/
CLK4
T5
O
Receive Channel Block/Receive Channel Block Clock.
This pin can be
configured to output either RCHBLK or RCHCLK. RCHBLK is a user-
programmable output that can be forced high or low during any of the 24 T1 or 32
E1 channels. It is synchronous with RCLK when the receive-side elastic store is
disabled. It is synchronous with RSYSCLK when the receive-side elastic store is
enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller
in applications where not all channels are used such as fractional service, 384kbps
service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-
and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
RCHCLK.
RCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during
the LSB of each channel. It is synchronous with RCLK when the receive-side
elastic store is disabled. It is synchronous with RSYSCLK when the receive-side
elastic store is enabled. It is useful for parallel-to-serial conversion of channel data.
Backplane Clock.
Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK
from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an
external reference clock. This allows for the IBO clock to reference from external
source or T1J1E1 recovered clock or the MCLK oscillator.
BPCLK
E8
O
MICROPROCESSOR INTERFACE
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
C8
A8
B8
F8
B9
A9
C9
D9
E9
F9
B10
A10
C10
T9
N9
M9
R8
T8
P8
L9
N8
I
Address [12:0].
This bus selects a specific register in the DS26524 during
read/write access. A12 is the MSB and A0 is the LSB.
I
Data [7:0].
This 8-bit, bidirectional data bus is used for read/write access of the
DS26524 information and control registers. D7 is the MSB and D0 is the LSB.
CSB
T7
I
Chip-Select Bar.
This active-low signal is used to qualify register read/write
accesses. The
RDB/DSB
and
WRB
signals are qualified with
CSB.
RDB
/
DSB
M8
I
Read-Data Bar/Data-Strobe Bar.
This active-low signal along with
CSB
qualifies
read access to one of the DS26524 registers. The DS26524 drives the data bus
with the contents of the addressed register while
RDB
and
CSB
are low.
Write-Read Bar/Read-Write Bar.
This active-low signal along with
CSB
qualifies
write access to one of the DS26524 registers. Data at D[7:0] is written into the
addressed register at the rising edge of
WRB
while
CSB
is low.
Interrupt Bar.
This active-low, open-drain output is asserted when an unmasked
interrupt event is detected.
INTB
will be deasserted when all interrupts have been
acknowledged and serviced. Extensive mask bits are provided at the global level,
framer, LIU, and BERT level.
WRB
/
RWB
R7
I
INTB
R9
U
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26524_07 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Quad T1/E1/J1 Transceiver
DS26524DK 功能描述:網(wǎng)絡(luò)開(kāi)發(fā)工具 DS26524 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類(lèi)型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類(lèi)型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS26524G 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26524G+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26524GA4 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray