
DS26519 16-Port T1/E1/J1 Transceiver
113 of 310
FRAMER REGISTER LIST
ADDRESS
0B1h
NAME
—
RRTS3
RRTS3
—
RRTS5
RHPBA
RHF
—
RBCS1
RBCS2
RBCS3
RBCS4
RCBR1
RCBR2
RCBR3
RCBR4
RSI1
RSI2
RSI3
RSI4
RGCCS1
RGCCS2
RGCCS3
RGCCS4
RCICE1
RCICE2
RCICE3
RCICE4
RBPCS1
RBPCS2
RBPCS3
RBPCS4
—
Global
Registers
(Section
10.3
)
TDMWE1
TDMWE2
TDMWE3
TDMWE4
TJBE1
TJBE2
TJBE3
TJBE4
TDDS1
TDDS2
TDDS3
THC1
THBSE
—
THC2
E1TSACR
—
DESCRIPTION
R/W
—
Reserved
Receive Real-Time Status Register 3 (T1 Mode)
Receive Real-Time Status Register 3 (E1 Mode)
Reserved
Receive Real-Time Status Register 5 (HDLC)
Receive HDLC Packet Bytes Available Register
Receive HDLC FIFO Register
Reserved
Receive Blank Channel Select Register 1
Receive Blank Channel Select Register 2
Receive Blank Channel Select Register 3
Receive Blank Channel Select Register 4 (E1 Mode Only)
Receive Channel Blocking Register 1
Receive Channel Blocking Register 2
Receive Channel Blocking Register 3
Receive Channel Blocking Register 4 (E1 Mode Only)
Receive-Signaling Reinsertion Enable Register 1
Receive-Signaling Reinsertion Enable Register 2
Receive-Signaling Reinsertion Enable Register 3
Receive-Signaling Reinsertion Enable Register 4 (E1 Mode Only)
Receive Gapped Clock Channel Select Register 1
Receive Gapped Clock Channel Select Register 2
Receive Gapped Clock Channel Select Register 3
Receive Gapped Clock Channel Select Register (E1 Mode Only)
Receive Channel Idle Code Enable Register 1
Receive Channel Idle Code Enable Register 2
Receive Channel Idle Code Enable Register 3
Receive Channel Idle Code Enable Register 4 (E1 Mode Only)
Receive BERT Port Channel Select Register 1
Receive BERT Port Channel Select Register 2
Receive BERT Port Channel Select Register 3
Receive BERT Port Channel Select Register 4 (E1 Mode Only)
Reserved
0B2h
R
0B3h
0B4h
0B5h
0B6h
—
R
R
R
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
0B7h–0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
0CAh
0CBh
0CCh
0CDh
0CEh
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h–0EFh
0F0h–0FFh
See the Global Register list in
Table 10-3
. Note that this space is
“Reserved” in Framers 2 to 8.
R/W
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
110h
111h
112h
113h
114h
Transmit Digital Milliwatt Enable Register 1 (T1 and E1 Modes)
Transmit Digital Milliwatt Enable Register 2 (T1 and E1 Modes)
Transmit Digital Milliwatt Enable Register 3 (T1 and E1 Modes)
Transmit Digital Milliwatt Enable Register 4 (T1 and E1 Modes)
Transmit Jammed Bit Eight Stuffing Register 1
Transmit Jammed Bit Eight Stuffing Register 2
Transmit Jammed Bit Eight Stuffing Register 3
Transmit Jammed Bit Eight Stuffing Register 4
Transmit DDS Zero Code Register 1
Transmit DDS Zero Code Register 2
Transmit DDS Zero Code Register 3
Transmit HDLC Control Register 1
Transmit HDLC Bit Suppress Register
Reserved
Transmit HDLC Control Register 2
E1 Transmit Sa-Bit Control Register (E1 Mode)
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
—
115h–117h