參數(shù)資料
型號: DS26324GNA3+
廠商: Maxim Integrated Products
文件頁數(shù): 84/120頁
文件大小: 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 16/16
規(guī)程: LIN
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
包裝: 托盤
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
66 of 120
6.1.3
Individual LIU Register Bank
The ADDP register must be set to 01h to access this bank.
Register Name:
IJAE
Register Description:
Individual Jitter Attenuator Enable
Register Address (LIUs 1–8):
00h
Bit #
7
6
5
4
3
2
1
0
Name
IJAE8
IJAE7
IJAE6
IJAE5
IJAE4
IJAE3
IJAE2
IJAE1
Default
0
Register Address (LIUs 9–16):
20h
Bit #
7
6
5
4
3
2
1
0
Name
IJAE16
IJAE15
IJAE14
IJAE13
IJAE12
IJAE11
IJAE10
IJAE9
Default
0
Bits 7 to 0: Individual Jitter Attenuator Enable Channel n (IJAEn). When this bit is set, the LIU jitter attenuator
n is enabled. Note that if the GC.JAE register bit is set, this register will be ignored.
Register Name:
IJAPS
Register Description:
Individual Jitter Attenuator Position Select
Register Address (LIUs 1–8):
01h
Bit #
7
6
5
4
3
2
1
0
Name
IJAPS8
IJAPS7
IJAPS6
IJAPS5
IJAPS4
IJAPS3
IJAPS2
IJAPS1
Default
0
Register Address (LIUs 9–16):
21h
Bit #
7
6
5
4
3
2
1
0
Name
IJAPS16
IJAPS15
IJAPS14
IJAPS13
IJAPS12
IJAPS11
IJAPS10
IJAPS9
Default
0
Bits 7 to 0: Individual Jitter Attenuator Position Select Channel n (IJAPSn). When this bit is set high, the jitter
attenuator is in the receive path n; when this bit is default or set low the jitter attenuator is in the transmit path n.
Note that if the GC.JAE register bit is set, this register will be ignored.
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