參數(shù)資料
型號: DS26324GN+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 73/120頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 500
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 16/16
規(guī)程: LIN
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應商設備封裝: 256-CSBGA(17x17)
包裝: 帶卷 (TR)
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
56 of 120
Register Name:
GC
Register Description:
Global Configuration
Register Address (LIUs 1–8):
0Fh
Bit #
7
6
5
4
3
2
1
0
Name
RIMPMS
AISEL
SCPD
CODE
JADS
CRIMP
JAPS
JAE
Default
0
Note: CRIMP controls all 16 LIUs. All other bits are for LIUs 1–8 only.
Bit 7: Receive Impedance Mode Select (RIMPMS). When this bit is set, fully internal impedance match mode is
selected, so RTIP and RRING require no external resistor. If this bit is set, the receiver line transformer must be a
1:1 turns ratio and the RTR bit set. When reset, external termination mode is selected and an external resistor is
required to terminate the receive line. This external resistor will be adjusted internally to the correct termination
value if partially internal impedance matching is turned on (TS.RIMPON = 1).
Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the system side upon detecting
LOS for each channel. The individual LIU register IAISEL settings will be ignored when this bit is set. When reset,
the IAISEL register will have control.
Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the short-circuit protection is disabled for all the
transmitters. The individual LIU register ISCPD settings will be ignored when this bit is set. When reset, the ISCPD
register will have control.
Bit 4: Code (CODE). If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored
when this bit is set. If reset, the LCS register will have control.
Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The
settings in the IJAFDS register will be ignored if this register is set. If reset the IJAFDS register will have control.
Bit 2: Calibrate Receive Internal Termination (CRIMP). A low-to-high transition on this bit initiates a calibration
cycle for the receive internal termination. This requires a 16k
±1% resistor on the RESREF pin. Bit 2 of the GC
register at address 0x2F must also be set to enable calibration. While this bit is set, RSL4.4 (0x0F in individual
bank) will indicate the status of the calibration cycle.
Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the jitter attenuator will be in the
receive path and when default or set low in the Transmit path. These settings can be changed for an individual LIU
by settings in the IJAPS register. Note that when bit JAE is set, the settings in the IJAPS register will be ignored.
Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the jitter attenuator is enabled. The settings in the IJAE
register will be ignored if this register is set. If reset, the IJAE register will have control.
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