參數(shù)資料
型號: DS26324GN+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 30/120頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 16/16
規(guī)程: LIN
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
包裝: 帶卷 (TR)
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
17 of 120
5 FUNCTIONAL DESCRIPTION
5.1
Port Operation
5.1.1
Serial Port Operation
Setting MODESEL = ‘low’ enables the serial bus interface on the DS26324. Port read/write timing is unrelated to
the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 9.3 for the
AC timing of the serial port. All serial port accesses are LSB first when BSWP pin is high and MSB first when
BSWP is low. Figure 5-1 to Figure 5-3 show operation with LSB first.
This port is compatible with the SPI interface defined for Motorola Processors. An example of this is the MMC2107
from Motorola.
Reading or writing to the internal registers requires writing one address/command byte prior to transferring register
data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write
(0). The next 6 bits identify the register address (A1 to A6) (A7 is ignored).
All data transfers are initiated by driving the CSB input low. When CLKE is low, SDO data is output on the rising
edge of SCLK and when CLKE is high, data is output on the falling edge of SCLK. Data is held until the next falling
or rising edge. All data transfers are terminated if CSB input transitions high. Port control logic is disabled and SDO
is tri-stated when CSB is high. SDI is always sampled on the rising edge of SCLK.
Figure 5-1. Serial Port Operation for Write Access
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CSB
0
A1
A2
A3
A4
A5
A
6
x
(adrs
msb)
SDI
SDO
D1
D2
D3
D4
D5
D7
(lsb)
(msb)
DO
D6
(lsb)
WRITE ACCESS ENABLED
Figure 5-2. Serial Port Operation for Read Access with CLKE = 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
A1
A2
A3
A4
A5
D1
D2
D3
D4
D5
D6
SCLK
SDI
SDO
CSB
(lsb)
(msb)
D0
(lsb)
D7
(msb)
A6
X
Read
Access
Enabled
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