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參數(shù)資料
| 型號： | DS2483R+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/29頁 |
| 文件大小： | 0K |
| 描述： | IC I2C TO 1WIRE BRIDGE SOT23-6 |
| 產(chǎn)品培訓模塊： | Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 系列： | * |
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14
Maxim Integrated
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
1-Wire Reset
Figure 4. 1-Wire Reset/Presence-Detect Cycle
Command Code
B4h
Command Parameter
None
Description
Generates a 1-Wire reset/presence-detect cycle at the 1-Wire line (Figure 4). The state of
the 1-Wire line is sampled at tSI and tMSP and the result is reported to the host processor
through the Status register bits PPD and SD.
Typical Use
To initiate or end any 1-Wire communication sequence.
Restriction
1-Wire activity must have ended before the DS2483 can process this command. Strong
pullup (see the SPU bit) should not be used in conjunction with the 1-Wire Reset command.
If SPU is enabled, the PPD bit may not be valid and may cause a violation of the device’s
absolute maximum rating.
Error Response
Command code is not acknowledged if 1WB = 1 at the time the command code is received
and the command is ignored.
Command Duration
2 O tRSTL + maximum 262.5ns, counted from the falling SCL edge of the command code
acknowledge bit.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Read Pointer Position
Status register (for busy polling).
Status Bits Affected
1WB (set to 1 for 2 O tRSTL), PPD is updated at tRSTL + tMSP, SD is updated at tRSTL + tSI.
Device Configurations Affected
1WS, APU, SPU apply.
Port Configurations Affected
tRSTL, tMSP, tW0L, tREC0, and RWPU current values apply.
PULLUP (SEE FIGURE 2)
DS2483 PULLDOWN
1-Wire SLAVE PULLDOWN
VCC
VIH1
VIL1
0V
RESET PULSE
PRESENCE/SHORT DETECT
tRSTL
tSI
tMSP
tRSTH
tF1
PRESENCE PULSE
APU CONTROLLED
EDGE
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| DS2484Q+T | 制造商:Maxim Integrated Products 功能描述: |
| DS2484R+T | 制造商:Maxim Integrated Products 功能描述: |
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