- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗11565 > DS2483R+T (Maxim Integrated Products)IC I2C TO 1WIRE BRIDGE SOT23-6 PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | DS2483R+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 13/29闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC I2C TO 1WIRE BRIDGE SOT23-6 |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 绯诲垪锛� | * |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)鐣�(d膩ng)鍓嶇13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)
20
Maxim Integrated
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
I2C Definitions
The following terminology is commonly used to describe
Bus Idle or Not Busy: Both SDA and SCL are inac-
tive and in their logic-high states.
START Condition: To initiate communication with a
slave, the master must generate a START condition.
A START condition is defined as a change in state of
SDA from high to low while SCL remains high.
STOP Condition: To end communication with a
slave, the master must generate a STOP condition. A
STOP condition is defined as a change in state of SDA
from low to high while SCL remains high.
Repeated START Condition: Repeated STARTs are
commonly used for read accesses to select a specific
data source or address from which to read. The mas-
ter can use a repeated START condition at the end
of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START
condition is generated the same way as a normal
START condition, but without leaving the bus idle after
a STOP condition.
Data Valid: With the exception of the START and
STOP condition, transitions of SDA can occur only
during the low state of SCL. The data on SDA must
remain valid and unchanged during the entire high
pulse of SCL plus the required setup and hold time
(tHD:DAT after the falling edge of SCL and tSU:DAT
before the rising edge of SCL; see Figure 9). There is
one clock pulse per bit of data. Data is shifted into the
receiving device during the rising edge of SCL pulse.
When finished with writing, the master must release
the SDA line for a sufficient amount of setup time
ing edge of SCL to start reading. The slave shifts out
each data bit on SDA at the falling edge of the previ-
ous SCL pulse and the data bit is valid at the rising
edge of the current SCL pulse. The master generates
all SCL clock pulses, including those needed to read
from a slave.
Acknowledge: Typically a receiving device, when
addressed, is obliged to generate an acknowledge
after the receipt of each byte. The master must
generate a clock pulse that is associated with this
acknowledge bit. A device that acknowledges must
pull SDA low during the acknowledge clock pulse
in such a way that SDA is stable low during the high
period of the acknowledge-related clock pulse plus
the required setup and hold time (tHD:DAT after the
falling edge of SCL and tSU:DAT before the rising
edge of SCL).
Figure 9. I2C Timing Diagram
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP
START
REPEATED
START
SPIKE
SUPPRESSION
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| 73S8024RN-ILR/F1 | IC SMART CARD INTERFACE 28SOIC |
| 73S8023C-IM/F | IC SMART CARD INTERFACE 32-QFN |
| 73S8024RN-IL/F1 | IC SMART CARD INTERFACE 28SOIC |
| 73S8024C-IL/F | IC SMART CARD INTERFACE 28-SOIC |
| PIC16C54CT-04I/SS | IC MCU OTP 512X12 20SSOP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| DS2484Q+T | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪: |
| DS2484R+T | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪: |
| DS2490 | 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū:Maxim Integrated Products 鍔熻兘鎻忚堪:USB to 1-Wire Bridge Chip |
| DS2490S | 鍔熻兘鎻忚堪:鎺ュ彛 - 灏堢敤 RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝侀鍨�:1080p60 Image Sensor Receiver 宸ヤ綔闆绘簮闆诲:1.8 V 闆绘簮闆绘祦:89 mA 鏈€澶у姛鐜囪€楁暎: 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:BGA-59 |
| DS2490S+ | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:USB TO 1-WIRE BRIDGE 24SOIC W - Rail/Tube 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:USB 1-W BRIDGE CHIP 24-SO LF 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:Bulk |
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
