
DS2450
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MEMORY MAP PAGE 2, ALARM SETTINGS
Figure 5c
Address
bit 7
bit 6
10
MSBL–A
A
11
MSBH–A
A
12
MSBL–B
B
MSBH–B
B
bit 5
A
bit 4
A
bit 3
A
bit 2
A
bit 1
A
bit 0
LSBL–A
A
A
A
A
A
LSBH–A
B
B
B
B
B
LSBL–B
13
14
15
16
17
B
B
B
B
B
LSBH–B
MSBL–C
C
C
C
C
C
C
LSBL–C
MSBH–C
C
C
C
C
C
C
LSBH–C
MSBL–D
D
D
D
D
D
D
LSBL–D
MSBH–D
D
D
D
D
D
D
LSBH–D
The registers for the alarm threshold voltages of each
channel are located in memory page 2 with the low
threshold being at the lower address (Figure 5c). The
power–on default thresholds are 00h for low alarm and
FFh for high alarm. The alarm settings are always eight
bits. For a resolution higher or equal to eight bits the
alarm flag will be set if the eight most significant bits of
the conversion result yield a number higher than stored
in the high alarm register (AFH) or lower than stored in
the low alarm register (AFL). For a resolution lower than
eight bits the least significant bits of the alarm registers
are ignored.
There is a fourth memory page in the address range of
18 to 1F used during calibration at the factory. This
memory page is accessible to the user through the
Read Memory and Write Memory commands. Chang-
ing the data of this page arbitrarily will de–calibrate the
A/D converter or make the device nonfunctional until it
undergoes a power–on reset. However, if the device is
V
CC
powered one can keep the analog circuitry perma-
nently active by writing a value of 80 hex to memory
address 1C after power–up. This eliminates the offset
time otherwise needed with each CONVERT command
for the internal bandgap reference to stabilize. See the
description of the CONVERT command for details.
FUNCTION COMMANDS
The Function Command Flow Chart (Figure 6)
describes the protocols necessary for accessing the
device registers. Since the memory map of the DS2450
is small compared to the 16–bit addressing capabilities
the 11 most significant bits of the address will be forced
to 0 before they enter the CRC–generator. The commu-
nication between master and DS2450 takes place either
at regular speed (default, OD = 0) or at Overdrive Speed
(OD = 1). If not explicitly set into Overdrive mode the
device assumes regular speed.
READ MEMORY [AAH]
The Read Memory command is used to read conversion
results, control/status data and alarm settings. The bus
master follows the command byte with a two byte
address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a
starting byte location within the memory map. With
every subsequent read data time slot the bus master
receives data from the DS2450 starting at the supplied
address and continuing until the end of an eight–byte
page is reached. At that point the bus master will receive
a 16–bit CRC of the command byte, address bytes and
data bytes. This CRC is computed by the DS2450 and
read back by the bus master to check if the command
word, starting address and data were received cor-
rectly. If the CRC read by the bus master is incorrect, a
Reset Pulse must be issued and the entire sequence
must be repeated.
Note that the initial pass through the Read Memory flow
chart will generate a 16–bit CRC value that is the result
of clearing the CRC–generator and then shifting in the
command byte followed by the two address bytes, and
finally the data bytes beginning at the first addressed
memory location and continuing through to the last byte
of the addressed page. Subsequent passes through the
Read Memory flow chart will generate a 16–bit CRC that
is the result of clearing the CRC–generator and then
shifting in the new data bytes starting at the first byte of
the next page.