
DS2450
091598 20/23
CRC HARDWARE DESCRIPTION AND POLYNOMIAL
Figure 12
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
5TH
STAGE
6TH
STAGE
7TH
STAGE
8TH
STAGE
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
POLYNOMIAL = X
16
+ X
15
+ X
2
+ 1
9TH
STAGE
10TH
STAGE
11TH
STAGE
12TH
STAGE
13TH
STAGE
14TH
STAGE
15TH
STAGE
16TH
STAGE
X
9
X
10
X
11
X
12
X
13
X
14
X
15
INPUT DATA
X
16
CRC
OUTPUT
CRC–GENERATION
With the DS2450 there are two different types of CRCs
(Cyclic Redundancy Checks). One CRC is a 8–bit type
and is stored in the most significant byte of the 64–bit
ROM. The bus master can compute a CRC value from
the first 56 bits of the 64–bit ROM and compare it to the
value stored within the DS2450 to determine if the ROM
data has been received error–free by the bus master.
The equivalent polynomial function of this CRC is X
8
+
X
5
+ X
4
+ 1. This 8–bit CRC is received in the true (non
inverted) form when reading the ROM of the DS2450. It
is computed once at the factory and lasered into the
ROM.
The other CRC is a 16–bit type, generated according to
the standardized CRC16 polynomial function X
16
+
X
15
+ X
2
+ 1. This CRC is used to safeguard data when
reading from or writing to the device’s memory. It is the
same type of CRC as is used with NV RAM based iBut-
tons to safeguard data packets of the iButton File Struc-
ture. In contrast to the 8–bit CRC, the 16–bit CRC is
always returned in the complemented (inverted) form. A
CRC–generator inside the DS2450 chip (Figure 12) will
calculate a new 16–bit CRC at every situation shown in
the command flow chart of Figure 6.
The DS2450 provides this CRC value to the bus master
to validate the transfer of command, address, and data
to and from the bus master. When reading the memory,
the 16–bit CRC is transmitted when the end of each
8–byte memory page is reached. At the initial pass
through the Read Memory flow chart the 16–bit CRC will
be generated by clearing the CRC–generator, shifting in
the command byte, low address, high address and the
data bytes beginning at the first addressed memory
location and continuing until the last byte of the
addressed memory page is reached. Subsequent
passes through the Read Memory flow chart will gener-
ate a 16–bit CRC that is the result of clearing the CRC–
generator and then shifting in the new data bytes start-
ing at the first byte of the next page and continuing until
the last byte of the page is reached.
When writing to the DS2450, the bus master receives a
16–bit CRC to verify the correctness of the data transfer
before the device copies the data byte to its memory.
With the initial pass through the Write Memory flow chart
the 16–bit CRC will be generated by clearing the CRC–
generator, shifting in the command, address low,
address high and the data byte. Subsequent passes
through the Write Memory flow chart due to the DS2450
automatically incrementing its address counter will gen-
erate an 16–bit CRC that is the result of loading (not
shifting) the new (incremented) address into the CRC–
generator and then shifting in the new data byte.
For more details on generating CRC values including
example implementations in both hardware and soft-
ware, see the Book of DS19xx iButton Standards.