
DS2450
091598 5/23
The control and status information for all channels is
located in memory page 1 (Figure 5b). As for the conver-
sion read–out, each channel has assigned 16 bits. The
four least significant bits, called RC3 to RC0, are an
unsigned binary number that represents the number of
bits to be converted. A code of 1111 (15 decimal) will
generate a 15–bit result. For a full 16–bit conversion the
code number needs to be 0000. The next two bits
beyond RC3 will always read 0. They have no function
and cannot be changed to 1s.
The next bits, OC (output control) and OE (enable out-
put) control the alternate use of a channel as output. For
normal operation as analog input the OE bit of a channel
needs to be 0, rendering the OC bit to a don’t care. With
OE set to 1, a 0 for OC will make the channel’s output
transistor conducting, a 1 for OC will switch the transis-
tor off. With a pull–up resistor to a positive voltage, for
example, the OC bit will directly translate into the volt-
age equivalent of its logic state. Enabling the output
does not disable the analog input. Conversions remain
possible, but will result in values close to 0 if the transis-
tor is conducting.
The IR bit in the second byte of a channel’s control and
status memory selects the input voltage range. With IR
set to 0, the highest possible conversion result is
reached at 2.55V. Setting IR to 1 requires an input volt-
age of 5.10V for the same result. The next bit beyond IR
has no function. It will always read 0 and cannot be
changed to 1.
The next two bits, AEL alarm enable low and AEH alarm
enable high, control whether the device will respond to
the Conditional Search command (see ROM Functions)
if a conversion results in a value higher (AEH) than or
lower (AEL) than the channel’s alarm threshold voltage
as specified in the alarm settings. The alarm flags AFL
(low) and AFH (high) tell the bus master whether the
channel’s input voltage was beyond the low or high
threshold at the latest conversion. These flags are
cleared automatically if a new conversion reveals a
non–alarming value. They can alternatively be written to
0 by the bus master without a conversion.
The next bit of a channel’s control and status memory
always reads 0 and cannot be changed to 1. The POR
bit (power on reset) is automatically set to 1 as the
device performs a power–on reset cycle. As long as this
bit is set the device will always respond to the Condi-
tional Search command in order to notify the bus master
that the control and threshold data is no longer valid.
After powering–up the POR bit needs to be written to 0
by the bus master. This may be done together with
restoring the control and threshold data. It is possible for
the bus master to write the POR bit to a 1. This will make
the device participate in the conditional search but will
not
generate a reset cycle. Since the POR bit is related
to the device and not channel–specific the value written
with the most recent setting of an input range or alarm
enable applies. The power–on default setting for the
control/status data is 08h for the first and 8Ch for the
second byte of each channel.
MEMORY MAP PAGE 1, CONTROL/STATUS DATA
Figure 5b
Address
bit 7
bit 6
08
OE–A
OC–A
09
POR
0
OE–B
OC–B
bit 5
0
bit 4
0
bit 3
RC3–A
bit 2
RC2–A
bit 1
RC1–A
bit 0
RC0–A
AFH–A
AFL–A
AEH–A
AEL–A
0
IR–A
0A
0B
0C
0D
0E
0
0
RC3–B
RC2–B
RC1–B
RC0–B
POR
0
AFH–B
AFL–B
AEH–B
AEL–B
0
IR–B
OE–C
OC–C
0
0
RC3–C
RC2–C
RC1–C
RC0–C
POR
0
AFH–C
AFL–C
AEH–C
AEL–C
0
IR–C
OE–D
OC–D
0
0
RC3–D
RC2–D
RC1–D
RC0–D
0F
POR
0
AFH–D
AFL–D
AEH–D
AEL–D
0
IR–D