DS2406
30 of 30
PIO SINK CURRENT
10 mA
20 mA
30 mA
40 mA
50 mA
60 mA
70 mA
80 mA
90 mA
100 mA
ISA, ISB
@ 0.4V
VPUP
PIO-B
max.
min.
PIO-A
max.
min.
4V
5V
6V
2.8V
NOTES:
1.
All voltages are referenced to ground.
2.
V
PUP
, V
PUPA
, V
PUPB
= external pull-up voltage.
3.
Input load is to ground.
4.
An additional reset or communication sequence cannot begin until the reset high time has expired.
5.
Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1 μs of this falling edge and will remain valid for 14 μs minimum (15
μs total from falling edge on 1-Wire bus).
6.
V
IH
is a function of the chip-internal supply voltage. This voltage is determined by either the external
pull-up resistor and V
PUP
or the V
CC
supply, whichever is higher. Without V
CC
supply, V
IH
for either
PIO pin should always be greater than or equal to V
PUP
-0.3V.
7.
Capacitance on the data pin could be 800 pF when power is first applied. If a 5 k
resistor is used to
pull up the data line to V
PUP
, 5 μs after power has been applied the parasite capacitance will not affect
normal communications.
8.
t
RSTL
should be limited to maximum 5 ms. Otherwise a parasitically powered DS2406 may perform a
power-on reset.
9.
Input resistance is to ground.
10.
V
CC
must be at least 4.0V if it is to be connected during a programming pulse.
11.
If the current at PIO-A reaches 200 mA the gate voltage of the output transistor will be reduced to
limit the sink current to 200 mA. The user-supplied circuitry should limit the current flow through the
PIO-transistor to no more than 100 mA. Otherwise the DS2406 may be damaged.
12.
PIO-A has a controlled turn-on output. The indicated currents are DC values. At V
PUP
= 4.0V or
higher the sink current typically reaches 80% of its DC value 1 μs after turning on the transistor.
13.
Under certain low voltage conditions V
ILMAX
may have to be reduced to as much as 0.5V to always
guarantee a presence pulse.
14.
The accumulative duration of the programming pulses for each address must not exceed 5 ms.
15.
The optimal sampling point for the master is as close as possible to the end time of the 15
μ
s t
RDV
period without exceeding t
RDV
. For the case of a Read-one time slot, this maximizes the amount of
time for the pull-up resistor to recover the line to a high level. For a Read-zero time slot it ensures
that a read will occur before the fastest 1-Wire devices(s) release the line (t
RELEASE
= 0).