參數(shù)資料
型號(hào): DS2404S-001
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO16
封裝: 0.300 INCH, SOIC-16
文件頁(yè)數(shù): 30/31頁(yè)
文件大小: 1591K
代理商: DS2404S-001
DS2404
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Setting a write protect bit to a logic 1 will permanently write protect the corresponding counter and alarm
registers, all write protect bits, and additional bits in the control register. The write protect bits can not be
written in a normal manner (see “Write Protect/Programmable Expiration” section).
3
RO
Read Only
If a programmable expiration occurs and the read only bit is set to a logic 1, then the DS2404 becomes
read only. If a programmable expiration occurs and the read only bit is a logic 0, then only the 64-bit
lasered ROM can be accessed (see “Write Protect/Programmable Expiration” section).
4
OSC
Oscillator enable
This bit controls the crystal oscillator. When set to a logic 1, the oscillator will start operation. When the
oscillator bit is a logic 0, the oscillator will stop.
5
AUTO/ MAN
Automatic/ Manual Mode
When this bit is set to a logic 1, the interval timer is in automatic mode. In this mode, the interval timer is
enabled by the I/O line. When this bit is set to a logic 0, the interval timer is in manual mode. In this
mode the interval timer is enabled by the STOP/ START bit.
6
STOP/ START
Stop/ Start (in Manual Mode)
If the interval timer is in manual mode, the interval timer will start counting when this bit is set to a logic
0 and will stop counting when set to a logic 1. If the interval timer is in automatic mode, this bit has no
effect.
7
DSEL Delay Select Bit
This bit selects the delay that it takes for the cycle counter and the interval timer (in auto mode) to see a
transition on the I/O line. When this bit is set to a logic 1, the delay time is 123 + 2 ms. This delay allows
communication on the I/O line without starting or stopping the interval timer and without incrementing
the cycle counter. When this bit is set to a logic 0, the delay time is 3.5 ±0.5 ms.
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 6) describes the protocols necessary for accessing the
memory. Two examples follow the flowchart. Three address registers are provided as shown in Figure 5.
The first two registers represent a 16-bit target address (TA1, TA2). The third register is the ending
offset/data status byte (E/S).
The target address points to a unique byte location in memory. The first five bits of the target address
(T4:T0) represent the byte offset within a page. This byte offset points to one of 32 possible byte
locations within a given page. For instance, 00000b points to the first byte of a page where as 11111b
would point to the last byte of a page.
相關(guān)PDF資料
PDF描述
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