參數(shù)資料
型號(hào): DS2404S-001
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO16
封裝: 0.300 INCH, SOIC-16
文件頁數(shù): 17/31頁
文件大?。?/td> 1591K
代理商: DS2404S-001
DS2404
24 of 29
OPERATION MODES AND CONDITIONS Table 1
PORT USAGE
BATTERY OPERATE MODE
VCC OPERATE MODE (BATTERY BACKED)
1-Wire only
Float RST , DQ, CLK or tie to GND
DQ Voltage (3-wire)
≤ VBATO
DQ Voltage (3-wire)
≤ VCC +0.3V
3-Wire only
If unused: float I/O (1-Wire) or tie to GND; if used as counter input: see text
DQ Voltage (3-wire)
≤ VBATO
DQ Voltage (3-wire)
≤ VCC +0.3V
1-Wire and 3-wire
Dual Port Operation
1-Wire Port: finish each communication with a reset/presence sequence: when
idle: either keep I/O pulled high through a resistor or pull it low;
3-wire Port: when idle: keep RST and CLK low, keep DQ high or low or
floating
DUAL PORT OPERATION
The on-chip arbitration logic works on a first-come, first serve principle. Assuming that at one time both
ports are idle, the one port that becomes active prior to the other one is granted access. Activity on the
3-wire port begins as the voltage level on the RST input changes from low to high. The 1-Wire port is
considered active with the first falling edge detected after the presence pulse.
Attempting to communicate with the device through the port that temporarily has no access does not
affect communication through the other port. If communication on the 1-Wire port is initiated while the
3-wire port is active, the device will still respond to the reset pulse, but any subsequently transmitted
1-Wire command will be ignored. When reading the ROM or memory, for example, the response will
always be 1’s, indicating that access was denied. While the 1-Wire port is active, the 3-wire data line DQ
is in tristate mode. The always present resistor of approximately 60k
Ω pulls DQ low. The micro
connected to the 3-wire port will fight against this weak pulldown and, depending on its port
characteristics, possibly dominate the logical value on DQ.
Since writing to the memory of the DS2404 requires multiple steps with short periods where both ports
are inactive, additional measures are required. To avoid one port overwriting actions initiated by the other
port one should do the following:
Allow the microcontroller operating the 3-wire port to monitor the activity on the 1-Wire port. This could
be done by means of a retriggerable one-shot, for example. The microcontroller should wait for a break of
several milliseconds on the 1-Wire port before attempting communication through the 3-wire port.
In addition, data should be organized as data packets with a length byte at the beginning and a CRC check
at the end. Whenever one side has finished communication with the DS2404 it should write a token such
as a “null-packet” into the scratchpad. A null-packet consists of three bytes that represent a zero length
followed by a valid 16-bit CRC. As one port tries to communicate with the device, the first memory
function command should be a Read Scratchpad. Communication should only proceed if the null-packet
is found. Otherwise communication through the other port is not yet finished and one is likely to interfere
if one does not immediately release the port for the communication on the other port to resume. For
details on recommended data structures please refer to chapters 7 or 10 of the “Book of DS19xx iButton
Standards”.
相關(guān)PDF資料
PDF描述
DS2404B 0 TIMER(S), REAL TIME CLOCK, PDSO16
DS2404 0 TIMER(S), REAL TIME CLOCK, PDIP16
DS2405P SPECIALTY MEMORY CIRCUIT, PDSO6
DS2405 SPECIALTY MEMORY CIRCUIT, PBCY3
DS2405Z SPECIALTY MEMORY CIRCUIT, PDSO4
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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