參數(shù)資料
型號: DS2404B
英文描述: EconoRAM Time Chip
中文描述: EconoRAM時鐘芯片
文件頁數(shù): 2/28頁
文件大?。?/td> 663K
代理商: DS2404B
DS2404
2 of 28
020998
DETAILED PIN DESCRIPTION
PIN
SYMBOL
1,16
DESCRIPTION
Power input pins
for V
CC
operate mode. 2.8 to 5.5 volts operation.
Either pin can be used for V
CC
. Only one is required for normal
operation. (See V
BATO
pin description and “Power Control” section).
Interrupt output pin:
Open drain.
Reset input pin
for 3-wire operation. (See “Parasite Power” section.)
Data input/output pin
for 3-wire operation.
Data input/output
for 1-Wire operation: Open drain. (See “Parasite
Power” section.)
Clock input pin
for 3-wire operation.
No connection pins.
Ground pin:
Either pin can be used for ground.
Battery backup input pin
:
Battery voltage can be 2.8 to 5.5 volts.
(See V
BATO
pin description and “Power Control” section.)
Battery operate input pin
for 2.8 to 5.5 volt operation. The V
CC
&
V
BATB
pins must be grounded when this pin is used to power the chip.
(See “Power Control” section.)
1 Hz square wave output:
Open drain.
Crystal pins
.
Connections for a standard 32.768 kHz quartz crystal,
EPSON part number C-002RX or C-004R (be sure to request 6 pF
load capacitance).
NOTE:
X1 and X2 are very high impedance nodes. It is
recommended that they and the crystal be guard-ringed with ground
and that high frequency signals be kept away from the crystal area.
See Figure 18 and Application Note 58 for details.
V
CC
2
3
4
5
IRQ
RST
DQ
I/O
6
CLK
NC
GND
V
BATB
7,12
8,13
9
10
V
BATO
11
1Hz
X
1
,X
2
14,15
OVERVIEW
The DS2404 has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, 3) 4096-bit
SRAM, and 4) timekeeping registers. The timekeeping section utilizes an on-chip oscillator that is
connected to an external 32.768 kHz crystal. The SRAM and timekeeping registers reside in one
contiguous address space referred to hereafter as memory. All data is read and written least significant bit
first.
Two communication ports are provided, a 1-Wire port and a 3-wire port. A port selector determines
which of the two ports is being used. The communication ports and the ROM are parasite-powered via
I/O,
RST
, or V
CC
. This allows the ROM to be read in the absence of power. The ROM data is accessible
only through the 1-Wire port. The scratchpad and memory are accessible via either port.
If the 3-wire port is used, the master provides one of four memory function commands: 1) read memory,
2) read scratchpad, 3) write scratchpad, or 4) copy scratchpad. The only way to write memory is to first
write the scratchpad and then copy the scratchpad data to memory. (See Figure 6.)
If the 1-Wire port is used, the memory functions will not be available until the ROM function protocol
has been established. This protocol is described in the ROM functions flow chart (Figure 9). The master
must first provide one of five ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM,
4) skip ROM or 5) search interrupt. After a ROM function sequence has been successfully executed, the
memory functions are accessible and the master may then provide any one of the four memory function
commands (Figure 6.)
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