參數(shù)資料
型號: DS2404B
英文描述: EconoRAM Time Chip
中文描述: EconoRAM時(shí)鐘芯片
文件頁數(shù): 19/28頁
文件大?。?/td> 663K
代理商: DS2404B
DS2404
19 of 28
020998
Interrupts
If the DS2404 detects an alarm condition, it will automatically set the corresponding alarm flag (CCF,
ITF or RTF) in the Status Register. If the flag’s corresponding interrupt bit (
RST
,
ITE
or
RTE
) is enabled
(logic 0) an interrupt condition begins as the alarm goes off. The DS2404 signals the interrupt condition
by pulling the open drain
IRQ
output low. The interrupt condition ceases when the alarm flags are cleared
(i.e., the interrupt is acknowledged by reading the Status Register, address 200H) or if the corresponding
interrupt enable bit is disabled (set to logic 1).
Interrupts can also be generated on the 1-Wire port. Since communication and interrupt signaling share
the same pin, one has to distinguish between two types of interrupts: spontaneous interrupts, called type
1, and delayed interrupts, type 2. Spontaneous interrupts that have not yet occurred need to be (re-)armed
by a reset pulse after all communication on the 1-Wire bus has finished. A single falling slope on the 1-
Wire bus will disarm this type of interrupt. If an alarm condition occurs while the device is disarmed, at
first a type 2 interrupt will be produced.
Spontaneous interrupts are signaled by the DS2404 by pulling the data line low for 960 to 3840
μ
s as the
interrupt condition begins (Figure 12). After this long low pulse a presence pulse will follow. If the alarm
condition occurs just after the master has sent a reset pulse, i.e., during the high or low time of the
presence pulse, the DS2404 will not assert its Interrupt Pulse until the presence pulse is finished (Figure
13).
If the DS2404 cannot assert a spontaneous interrupt, either because the data line was not pulled high,
communication was in progress, or the interrupt was not armed, it will extend the next reset pulse to a
total length of 960 to 3840
μ
s (delayed interrupt). If the alarm condition occurs during the reset low time
of the reset pulse, the DS2404 will immediately assert its interrupt pulse; thus the total low time of the
pulse can be extended up to 4800
μ
s (Figure 14). If a DS2404 with a not previously signaled alarm
detects a power-on cycle on the 1-Wire bus, it will send a presence pulse and wait for the reset pulse sent
by the master to extend it and to subsequently issue a presence pulse (Figure 15). As long as an interrupt
has not been acknowledged by the master, the DS2404 will continue sending interrupt pulses.
The interrupt signaling discussed so far is valid for the first opportunity the device has to signal an
interrupt. It is not required for the master to acknowledge an interrupt immediately. If an interrupt is not
acknowledged, the DS2404 will continue signaling the interrupt with every reset pulse. To do so, DS2404
devices of Revision B4 (earlier production parts) will always use the waveform of the Type 2 Interrupt
(Figure 14). Devices of Revision B5 (current production) will either use the waveform of the Type 2
Interrupt (Figure 14) or the waveform of the Type 1A Interrupt (Figure 13). The waveform of the Type 2
Interrupt will be observed after a communication to a device other than the interrupting one; after
successful communication to the interrupting device (without acknowledging the interrupt) the waveform
of the Type 1A Interrupt will be found. The revision code of the DS2404 is appended to the
manufacturing date code which is printed on the top of the package right below the part number.
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