參數(shù)資料
型號: DS21Q50L-W+
廠商: Maxim Integrated Products
文件頁數(shù): 67/87頁
文件大?。?/td> 0K
描述: TXRX E1 QUAD CLK/DATA 100LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
功能: 收發(fā)器
接口: E1
電路數(shù): 4
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 230mA
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: *
其它名稱: 90-21Q50+LW0
DS21Q50
7 of 87
Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125s
frame, there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first.
These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is
identical to channel 1; time slot 1 is identical to channel 2; and so on. Each time slot (or channel) is made
up of eight bits that are numbered 1 to 8. Bit number 1, MSB, is transmitted first. Bit number 8, the LSB,
is transmitted last. The term “l(fā)ocked” is used to refer to two clock signals that are phase-locked or
frequency-locked or derived from a common clock (i.e., a 8.192MHz clock can be locked to a 2.048MHz
clock if they share the same 8kHz component). Throughout this data sheet, the following abbreviations
are used:
NAME
FUNCTION
FAS
Frame Alignment Signal
CAS
Channel Associated Signaling
MF
Multiframe
Si
International bits
CRC4
Cyclical Redundancy Check
CCS
Common Channel Signaling
Sa
Additional bits
E-Bit
CRC4 Error Bits
LOC
Loss of Clock
TCLK
This generally refers to the transmit rate clock and can reference an actual input
signal to the device (TCLK) or an internally derived signal used for transmission.
RCLK
This generally refers to the recovered network clock and can be a reference to an
actual output signal from the device or an internal signal.
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