參數(shù)資料
型號: DS21Q44TN
英文描述: MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes
中文描述: 增強(qiáng)的四素E1成幀器
文件頁數(shù): 59/105頁
文件大?。?/td> 620K
代理商: DS21Q44TN
DS21Q44
59 of 105
SYMBOL
POSITION
NAME AND DESCRIPTION
Sa5
TSaCR.3
Additional Bit 5 Insertion Control Bit.
0=do not insert data from the TSa5 register into the transmit data
stream.
1=insert data from the TSa5 register into the transmit data
stream.
Additional Bit 6 Insertion Control Bit.
0=do not insert data from the TSa6 register into the transmit data
stream.
1=insert data from the TSa6 register into the transmit data
stream.
Additional Bit 7 Insertion Control Bit.
0=do not insert data from the TSa7 register into the transmit data
stream.
1=insert data from the TSa7 register into the transmit data
stream.
Additional Bit 8 Insertion Control Bit.
0=do not insert data from the TSa8 register into the transmit data
stream.
1=insert data from the TSa8 register into the transmit data
stream.
Sa6
TSaCR.2
Sa7
TSaCR.1
Sa8
TSaCR.0
15. HDLC Controller for the Sa Bits or DS0
Each framer in the DS21Q44 has the ability to extract/insert data from/ into the Sa bit positions (Sa4 to
Sa8) or from/to any multiple of DS0 channels Each framer contains a complete HDLC controller and this
operation is covered in Section 15.1.
15.1 General Overview
Each framer contains a complete HDLC controller with 64–byte buffers in both the transmit and receive
directions. The HDLC controller performs all the necessary overhead for generating and receiving a
HDLC formatted message.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to
the HDLC data stream.
There are eleven registers that the host will use to operate and control the operation of the HDLC
controller. A brief description of the registers is shown in Table 15-1.
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