參數(shù)資料
型號： DS21Q44TN
英文描述： MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes
中文描述： 增強的四素E1成幀器
文件頁數(shù)： 33/105頁
文件大小： 620K
代理商： DS21Q44TN
DS21Q44
33 of 105
SYMBOL
POSITION
NAME AND DESCRIPTION
TESALGN
CCR5.5
Transmit Elastic Store Align.
Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section 13
for details.
Receive Channel Monitor Bit 4.
MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 9 for details.
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0.
LSB of the channel decode.
RCM4
CCR5.4
RCM3
RCM2
RCM1
RCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
CCR6: COMMON CONTROL REGISTER 6
(Address=1D Hex)
(MSB)
–
(LSB)
TESR
–
–
–
–
TCLKSRC
RESR
SYMBOL
POSITION
NAME AND DESCRIPTION
–
–
–
–
–
CCR6.7
CCR6.6
CCR6.5
CCR6.4
CCR6.3
CCR6.2
Not Assigned.
Should be set to zero when written
Not Assigned.
Should be set to zero when written
Not Assigned.
Should be set to zero when written
Not Assigned.
Should be set to zero when written
Not Assigned.
Should be set to zero when written
Transmit Clock Source Select.
This function allows the user
to internally select RCLK as the clock source for the transmit
side formatter.
0 = Transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
Receive Elastic Store Reset.
Setting this bit from a zero to a
one will force the receive elastic store to a depth of one frame.
Receive data is lost during the reset. Should be toggled after
RSYSCLK has been applied and is stable. Do not leave this bit
set high.
Transmit Elastic Store Reset.
Setting this bit from a zero to a
one will force the transmit elastic store to a depth of one frame.
Transmit data is lost during the reset. Should be toggled after
TSYSCLK has been applied and is stable. Do not leave this bit
set high.
TCLKSRC
RESR
CCR6.1
TESR
CCR6.0
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