參數(shù)資料
型號(hào): DS21Q43AT
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁數(shù): 53/60頁
文件大?。?/td> 748K
代理商: DS21Q43AT
DS21Q43A
57 of 60
TRANSMIT SYSTEM SIDE AC TIMING Figure 12-9
NOTES:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is
enabled.
2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is
enabled.
AC CHARACTERISTICS -
NON-MULTIPLEXED PARALLEL (0
°C to 70°C; V
DD=5V
± 10% for DS21Q43AT;
PORT (MUX=0)
-40
°C to +85°C; V
DD=5V
± 10% for DS21Q43ATN)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Set Up Time for A0 to A6, FS0, FS1
Valid to CS Active
t1
0
ns
Set Up Time for CS Active to either
RD
, WR , or DS Active
t2
0
ns
Delay Time from either RD or DS
Active to Data Valid
t3
75
ns
Hold Time from either RD , WR , or DS
Inactive to CS Inactive
t4
0
ns
Hold Time from CS Inactive to Data
Bus 3-State
t5
5
20
ns
Wait Time from either WR
or DS
Active to Latch Data
t6
75
ns
Data Set Up Time to either WR or DS
Inactive
t7
10
ns
Data Hold Time from either WR or DS
Inactive
t8
10
ns
Address Hold Time
t9
10
ns
See Figures 13-10 to 13-13 for details.
相關(guān)PDF資料
PDF描述
DS21Q44T DATACOM, FRAMER, PQFP128
DS21Q44TN DATACOM, FRAMER, PQFP128
DS21Q48N DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q48 DATACOM, PCM TRANSCEIVER, PBGA144
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