參數(shù)資料
型號(hào): DS21Q43AT
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁(yè)數(shù): 23/60頁(yè)
文件大小: 748K
代理商: DS21Q43AT
DS21Q43A
3 of 60
DS21Q43A BLOCK DIAGRAM Figure 1-1
READER’S NOTE
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
timeslots in an E1 system which are numbered 0 to 31. Timeslot 0 is transmitted first and received first.
These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is
identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made
up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is
the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS
Frame Alignment
CRC4
Cyclical Redundancy Check
CAS
Channel Associated
CCS
Common Channel Signaling
Signaling
MF
Multiframe
Sa
Additional bits
Si
International bits
E-bit
CRC4 Error bits
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