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參數(shù)資料
| 型號： | DS21Q43AT |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 40/60頁 |
| 文件大?。?/td> | 748K |
| 代理商： | DS21Q43AT |
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DS21Q43A
40 of 60
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB) (LSB)
CH20
CH4
CH19
CH3
CH24
CH8
CH23
CH7
CH28
CH12
CH27
CH11
CH32
CH16
CH31
CH15
*=CH1 and CH17 should be set to 1 to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
10.0 ELASTIC STORES OPERATION
Each framer within the DS21Q43A contains dual two-frame (512 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544 MHz or
2.048 MHz or a multiple thereof up to 8.192 MHz). Both elastic stores contain full controlled slip
capability which is necessary for this second purpose. The elastic stores can be forced to a known depth
via the Elastic Store Reset bit (CCR3.4). Toggling the CCR3.4 bit forces the read and write pointers into
opposite frames. Both elastic stores within the DS21Q43A are fully independent and no restrictions apply
to the sourcing of the various clocks that are applied to them. The transmit side elastic store can be
enabled whether the receive elastic store is enabled or disabled and vice versa. Also, each elastic store can
interface to either a 1.544 MHz or 2.048 MHz backplane without regard to the backplane rate the other
elastic store is interfacing to.
10.1 Receive Side
If the receive side elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz
(RCR2.2=0) or 2.048 MHz (RCR2.2=1) clock at the RSYSCLK pin. The user has the option of either
providing a frame sync at the RSYNC pin (RCR1.5=1) or having the RSYNC pin provide a pulse on
frame boundaries (RCR1.5=0). If the user wishes to obtain pulses at the frame boundary, then RCR1.6
must be set to 0 and if the user wishes to have pulses occur at the multiframe boundary, then RCR1.6
must be set to 1. The DS21Q43A will always indicate frame boundaries via the RFSYNC output whether
the elastic store is enabled or not. If the elastic store is enabled, then either CAS (RCR1.7=0) or CRC4
(RCR1.7=1) multiframe boundaries will be indicated via the RMSYNC output. If the user selects to apply
a 1.544 MHz clock to the RSYSCLK pin, then every fourth channel of the received E1 data will be
deleted and an F-bit position (which will be forced to 1) will be inserted. Hence channels 1, 5, 9, 13, 17,
21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the received E1 data stream.
Also, in 1.544 MHz applications, the RCHBLK output will not be active in channels 25 through 32 (or in
other words, RCBR4 is not active). See Section 11 for more details. If the 512-bit elastic buffer either
fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data (256 bits) will
be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a 1. If the buffer fills, then a full frame of
data will be deleted and the SR1.4 and RIR.4 bits will be set to a 1.
10.2 Transmit Side
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR3.7. A 1.544 MHz (CCR3.1=0) or 2.048 MHz (CCR3.1=1) clock can be applied
to the TSYSCLK input. If the user selects to apply a 1.544 MHz clock to the TSYSCLK pin, then the data
sampled at TSER will be ignored every fourth channel. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29
(timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. The user must supply a 8 kHz frame sync pulse
to the TFSYNC input. See Section 11 for more details. Controlled slips in the transmit elastic store are
reported in the SR2.0 bit and the direction of the slip is reported in the RIR.6 and RIR.7 bits.
CH18
CH22
CH26
CH30
CH2
CH6
CH10
CH14
CH17*
CH21
CH25
CH29
CH1*
CH5
CH9
CH13
TCBR1
TCBR2
TCBR3
TCBR4
相關PDF資料 |
PDF描述 |
|---|---|
| DS21Q43ATN | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q44 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q44T | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q44TN | MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes |
| DS2251T-128-16 | CONNECTOR ACCESSORY |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q43AT+ | 功能描述:網(wǎng)絡控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q43ATN | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Quad E1 Framer |
| DS21Q43-ATN | 功能描述:網(wǎng)絡控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q44 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Enhanced QUAD E1 FRAMER |
| DS21Q44T | 功能描述:網(wǎng)絡控制器與處理器 IC Enhanced Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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