參數(shù)資料
型號(hào): DS21Q43AT
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 11/60頁(yè)
文件大?。?/td> 748K
代理商: DS21Q43AT
DS21Q43A
11 of 60
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7].
In non-multiplexed bus operation (MUX=0),
serves as the data bus. In multiplexed bus operation (MUX=1), serves as an 8-bit multiplexed
address/data bus.
Address Bus [A0 to A5].
In non-multiplexed bus operation (MUX=0), serves as the address bus. In
multiplexed bus operation (MUX=1), these pins are not used and should be tied low.
Bus Type Select [BTS].
Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the
RD
(DS), ALE(AS), and
WR
(R/
W
) pins. If BTS=1, then these pins
assume the function listed in parentheses ().
Read Input [
RD
] (Data Strobe [DS]).
Framer Selects [FS0 and FS1].
Selects which of the four framers to be accessed.
Chip Selects [
CS
].
Must be low to read or write to any of the four framers.
A6 or Address Latch Enable [ALE] (Address Strobe [AS]).
In non-multiplexed bus operation
(MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex
the bus on a positive-going edge.
Write Input [
WR
] (Read/Write [R/
W
]).
Positive Supply [V
DD
].
5.0 volts ± 0.5 volts.
Signal Ground [V
SS
].
0.0 volts.
DS21Q43A FRAMER DECODE
Table 1-5
FS1
0
0
1
1
FS0
0
1
0
1
FRAMER ACCESSED
#0
#1
#2
#3
相關(guān)PDF資料
PDF描述
DS21Q43ATN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44T Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44TN MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes
DS2251T-128-16 CONNECTOR ACCESSORY
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