參數(shù)資料
型號: DS21FT44
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁數(shù): 112/117頁
文件大?。?/td> 691K
代理商: DS21FT44
DS21FT44/DS21FF44
94 of 117
Figure 22-3. RECEIVE SIDE 1.544MHz BOUNDARY TIMING (With Elastic
Store Enabled)
Figure 22-4. RECEIVE SIDE 2.048MHz BOUNDARY TIMING (With Elastic
Store Enabled)
RSER
LSB MSB
F
MSB
LSB
RCHCLK
RSYNC / RMSYNC
RCHBLK
RSYSCLK
RSYNC
1
2
3
CHANNEL 23/31
CHANNEL 24/32
CHANNEL 1/2
4
Notes:
1. Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is
mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to one)
2. RSYNC is in the output mode (RCR1.5 = 0)
3. RSYNC is in the input mode (RCR1.5 = 1)
4. RCHBLK is programmed to block channel 24
RSER
LSB MSB
LSB
CHANNEL 1
RCHCLK
RSYNC / RMSYNC
RCHBLK
RSYSCLK
RSYNC
CHANNEL 31
CHANNEL 32
1
2
3
MSB
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0)
2. RSYNC is in the input mode (RCR1.5 = 1)
3. RCHBLK is programmed to block channel 1
4. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1
RSIG
D
CHANNEL 1
CHANNEL 31
CHANNEL 32
Note 4
A
B
C
D
AB
C
相關(guān)PDF資料
PDF描述
DS21Q352 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q354 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q41BT DATACOM, FRAMER, PQFP128
DS21Q42TN DATACOM, FRAMER, PQFP128
DS21Q42T DATACOM, FRAMER, PQFP128
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