參數(shù)資料
型號: DS21FT40
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 59/87頁
文件大?。?/td> 386K
代理商: DS21FT40
DS21FT40
59 of 87
HSR: HDLC STATUS REGISTER (Address=B1 Hex)
(MSB)
RPE
RPS
(LSB)
TMEND
RHALF
RNE
THALF
TNF
SYMBOLS
POSITION
NAME AND DESCRIPTION
HSR.7
HSR.6
Not Assigned. Should be set to zero.
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as
a CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RHIR register for details.
Receive Packet Start. Set when the HDLC controller detects
an opening byte. The setting of this bit prompts the user to
read the RHIR register for details.
Receive FIFO Half Full. Set when the receive 64–byte FIFO
fills beyond the half way point. The setting of this bit prompts
the user to read the RHIR register for details.
Receive FIFO Not Empty. Set when the receive 64–byte FIFO
has at least one byte available for a read. The setting of this bit
prompts the user to read the RHIR register for details.
Transmit FIFO Half Empty. Set when the transmit 64–byte
FIFO empties beyond the half way point. The setting of this
bit prompts the user to read the THIR register for details.
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO
has at least one byte available. The setting of this bit prompts
the user to read the THIR register for details.
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this
bit prompts the user to read the THIR register for details.
RPE
RPS
HSR.5
RHALF
HSR.4
RNE
HSR.3
THALF
HSR.2
TNF
HSR.1
TMEND
HSR.0
NOTE:
The RPE, RPS, and TMEND bits are latched and will be cleared when read.
HIMR: HDLC INTERRUPT MASK REGISTER (Address=B2 Hex)
(MSB)
RPE
RPS
RHALF
(LSB)
TMEND
RNE
THALF
TNF
SYMBOLS
POSITION
NAME AND DESCRIPTION
HIMR.7
HIMR.6
Not Assigned. Should be set to zero.
Receive Packet End.
0 = interrupt masked.
1 = interrupt enabled.
Receive Packet Start.
0 = interrupt masked.
1 = interrupt enabled.
RPE
RPS
HIMR.5
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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