參數(shù)資料
型號: DS21FT40
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 40/87頁
文件大小: 386K
代理商: DS21FT40
DS21FT40
40 of 87
the framer should be programmed to count BPVs when receiving AMI code and to count CVs when
receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions.
The counter saturates at 65,535 and will not rollover. The bit error rate on a E1 line would have to be
greater than 10** –2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB)
V15
V14
V13
V12
V11
V7
V6
V5
V4
V3
(LSB)
V8
V0
V10
V2
V9
V1
VCR1
VCR2
SYMBOLS
V15
V0
POSITION
VCR1.7
VCR2.0
NAME AND DESCRIPTION
MSB of the 16–bit code violation count
LSB of the 10–bit code violation count
CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the
least significant word of a 10–bit counter that records word errors in the Cyclic Redundancy Check 4
(CRC4). Since the maximum CRC4 count in a one second period is 1000, this counter cannot saturate.
The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if
loss of multiframe sync occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB)
(note 1)
(note 1)
(note 1)
(note 1)
CRC7
CRC6
CRC5
CRC4
(LSB)
CRC8
CRC0
(note 1)
CRC3
(note 1)
CRC2
CRC9
CRC1
CRCCR1
CRCCR2
SYMBOLS
POSITION
NAME AND DESCRIPTION
CRC9
CRC0
CRCCR1.1
CRCCR2.0
MSB of the 10–Bit CRC4 error count
LSB of the 10–Bit CRC4 error count
NOTE:
1.
The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12–bit FAS error
counter.
E–Bit Counter
E–bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10–bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E–bit is set to zero. Since the maximum E–bit count in a one second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will
continue to count if loss of multiframe sync occurs at the CAS level.
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