參數(shù)資料
型號(hào): DS21FT40
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 53/87頁(yè)
文件大?。?/td> 386K
代理商: DS21FT40
DS21FT40
53 of 87
TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex)
(MSB)
Si
0
0
[Must be programmed with the 7 bit FAS word; the DS21FT40 does not automatically set these bits]
(LSB)
1
1
1
0
1
SYMBOLS
POSITION
NAME AND DESCRIPTION
Si
0
0
1
1
0
1
1
TAF.7
TAF.6
TAF.5
TAF.4
TAF.3
TAF.2
TAF.1
TAF.0
International Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
TNAF: TRANSMIT NON–ALIGN FRAME REGISTER (Address=21 Hex)
(MSB)
Si
1
A
Sa4
[Bit 2 must be programmed to one; the DS21FT40 does not automatically set this bit]
(LSB)
Sa8
Sa5
Sa6
Sa7
SYMBOLS
POSITION
NAME AND DESCRIPTION
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
TNAF.7
TNAF.6
TNAF.5
TNAF.4
TNAF.3
TNAF.2
TNAF.1
TNAF.0
International Bit.
Frame Non–Alignment Signal Bit.
Remote Alarm (used to transmit the alarm).
Additional Bit 4.
Additional Bit 5.
Additional Bit 6.
Additional Bit 7.
Additional Bit 8.
13.2 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME
On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the
Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4
Multiframe bit in Status Register 2 (SR2.1). The host can use the SR2.1 bit to know when to read these
registers. The user has 2 ms to retrieve the data before it is lost. The MSB of each register is the first
received. Please see the register descriptions below and the Transmit Data Flow diagram in Section 16
for more details. On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4
to TSa8) that via the Transmit Sa Bit Control Register (TSaCR), can be programmed to insert both Si and
Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status
Register 2 (SR2.5). The host can use the SR2.5 bit to know when to update these registers. It has 2 ms to
update the data or else the old data will be retransmitted. The MSB of each register is the first bit
transmitted. Please see the register descriptions below and the Transmit Data Flow diagram in Section 16
for more details.
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