參數資料
型號: DS21FF42N+
廠商: Maxim Integrated Products
文件頁數: 113/114頁
文件大?。?/td> 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: T1 調幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應商設備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
98 of 114
TRANSMIT SIDE ESF TIMING Figure 23-9
TRANSMIT SIDE BOUNDARY TIMING
(with elastic store disabled) Figure 23-10
12
34
5
6
7
8
9
1011 12 1314 15 16 17
18 19 20 21 22 23 24
FRAME#
1
2
3
4
6
7
TSYNC
TLCLK
TLINK
TLCLK
TLINK
Notes:
1. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0)
2. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1)
3. TSYNC in the multiframe mode (TCR2.3 = 1)
4. ZBTSI mode disabled (TCR2.5 = 0)
5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing
T1 streamif enabled via TCR1.2
6. ZBTSI mode is enabled (TCR2.5 = 1)
7. TLINK data (Z bits) is sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted
into the outgoing stream if enabled via TCR1.2
8. TLINK and TLCLK are not synchronous with TFSYNC
TCLK
TNEG
LSB
MSB
F
MSB
LSB
TCHCLK
TSYNC
TCHBLK
Notes:
1. There is a 10 TCLK delay fromTSER to TPOS/TNEG.
2. TSYNC is in the output mode (TCR2.2 = 1)
3. TSYNC is in the input mode (TCR2.2 = 0)
4. TCHBLK is programmed to block channel 2
5. Shown is TLINK/TLCLK in the ESF framing mode
TLCLK
TLINK
LSB
CHANNEL 1
TSYNC
Don't Care
3
TSIG
CHANNEL 1
CHANNEL 2
A
B
C/A
D/B
AB
C/A
D/B
2
5
4
TSER LSB
MSB
FMSB
CHANNEL 1
LSB
LSB MSB
CHANNEL 2
TPOS
CHANNEL 24
1
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