參數(shù)資料
型號: DS21FF42N+
廠商: Maxim Integrated Products
文件頁數(shù): 109/114頁
文件大?。?/td> 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
94 of 114
23.
TIMING DIAGRAMS
RECEIVE SIDE D4 TIMING Figure 23-1
RECEIVE SIDE ESF TIMING Figure 23-2
12
34
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FRAME#
RSYNC /
RFSYNC
RSYNC
1
2
RSYNC
3
RLCLK
RLINK
4
5
RLCLK
RLINK
6
7
Notes:
1. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is not enabled (RCR2.5 = 0)
2. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is enabled (RCR2.5 = 1)
3. RSYNC in the multiframe mode (RCR2.4 = 1)
4. ZBTSI mode disabled (RCR2.6 = 0)
5. RLINKdata (FDL bits) is updated one bit time before odd frames and held for two frames
6. ZBTSI mode is enabled (RCR2.6 = 1)
7. RLINKdata (Z bits) is updated one bit time before odd frames and held for four frames
8. RLINKand RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled
FRAME#
1
2345
678
9
10
11
12
1
23
45
RSYNC /
RFSYNC
1
RSYNC
RSYNC2
3
RLCLK
RLINK4
Notes:
1. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is not enabled (RCR2.5 = 0)
2. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is enabled (RCR2.5 = 1)
3. RSYNC in the multiframe mode (RCR2.4 = 1)
4. RLINKdata (Fs - bits) is updated one bit prior to even frames and held for two frames
5. RLINKand RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled
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