參數(shù)資料
型號: DS2174Q+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 6/24頁
文件大小: 0K
描述: IC BERT ENHANCED 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
功能: 增強型位誤碼率測試器(EBERT)
接口: E1,J1,T1
電路數(shù): 1
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 50mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
包括: 錯誤計數(shù)器,樣式發(fā)生器和檢測器
DS2174
14 of 24
Control Register 3 (Address = 2h)
(MSB)
(LSB)
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
SYMBOL
FUNCTION
PL7
Pattern Length Bit 7. Bit 7 of [8:0] end address of repetitive pattern data.
PL6
Pattern Length Bit 6. Bit 6 of [8:0] end address of repetitive pattern data.
PL5
Pattern Length Bit 5. Bit 5 of [8:0] end address of repetitive pattern data.
PL4
Pattern Length Bit 4. Bit 4 of [8:0] end address of repetitive pattern data.
PL3
Pattern Length Bit 3. Bit 3 of [8:0] end address of repetitive pattern data.
PL2
Pattern Length Bit 2. Bit 2 of [8:0] end address of repetitive pattern data.
PL1
Pattern Length Bit 1. Bit 1 of [8:0] end address of repetitive pattern data.
PL0
Pattern Length Bit 0. Bit 0 of [8:0] end address of repetitive pattern data.
Control Register 4 (Address = 3h)
(MSB)
(LSB)
TEST
CLK_INV
R/W
RAM
COUNT
SEED
PL8
SYMBOL
FUNCTION
TEST
Factory Use. Must be set to 0 for proper operation.
TEST
Factory Use. Must be set to 0 for proper operation.
CLK_INV
TCLKO Invert.
0 = TCLKO polarity is normal
1 = TCLKO polarity is inverted
R/W
Read/Write Select. This bit is used with the RAM bit to read or write the
RAM.
0 = Write to the RAM
1 = Read from the RAM
RAM
RAM Select. This bit should be set when repetitive pattern data is being
loaded into the RAM. See flowchart in Section 4 for a description of this
process.
0 = BERT state machine has control of the RAM
1 = Parallel port has read and write access to the RAM
COUNT
Select Bit for Registers Ah–Fh.
0 = Registers Ah–Fh refer to bit count registers.
1 = Registers Ah–Fh refer to error count registers.
SEED
Select Bit for Registers 5h–8h.
0 = Registers 5h–8h refer to tap select registers.
1 = Registers 5h–8h refer to preload seed registers.
PL8
Pattern Length Bit 8. Bit 8 of [8:0] End Address of Repetitive Pattern Data.
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