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參數(shù)資料
| 型號： | DS2174Q+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 0K |
| 描述： | IC BERT ENHANCED 44-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 功能： | 增強型位誤碼率測試器（EBERT） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 50mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 包括： | 錯誤計數(shù)器，樣式發(fā)生器和檢測器 |
DS2174
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1.2 Pattern Synchronization
1.2.1 Synchronization
The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error free
when the synchronizer is online. Once synchronized, an error density of 6 bits in 64 causes the receiver to
declare loss-of-pattern sync, set the RLOS bit, and the synchronizer comes back online.
1.2.2 Polynomial Synchronization
Synchronization to polynomial patterns take 50 + n clock cycles (14 + n in nibble mode, 8 + n in byte
mode), where n is the exponent in the polynomial that describes the pattern. Once synchronized, any bit
that does not match the polynomial is counted as a bit error.
1.2.3 Repetitive Pattern Synchronization
Synchronization to repetitive patterns can take several complete repetitions of the entire pattern. The
actual sync time depends on the nature of the pattern and the location of the synchronization pointer.
Errors that occur during synchronization could affect the sync time; at least one complete error-free
repetition must be received before synchronization is declared. Once synchronized, any bit that does not
match the pattern that is programmed in the on-board RAM is counted as a bit error.
1.3 Bit Error Rate (BER) Calculation
1.3.1 Counters
The bit counter is active at all times. Once synchronized, the error counters come online. The receiver has
large 48-bit count registers. These counters accumulate for 50,640 hours at the T1 line rate, 1.544MHz,
and 38,170 hours at the E1 line rate, 2.048MHz. At higher clock rates, the counters saturate quicker, but
at the T3 line rate, the counter still runs for almost 1500 hours, and at 155MHz it runs for 504 hours.
To accumulate BER data, the user toggles the LC bit at T = 0. This clears the accumulators and loads the
contents into the count registers. At T = 0, these results should be ignored. At this point, the device is
counting bits and bit errors. At the end of the specified time interval, the user toggles the LC bit again and
reads the count registers. These are the valid results used to calculate a bit error rate. Remember, the bit
counter is really counting clocks, so in nibble and byte modes the bit counter value needs to be multiplied
by 4 or 8 to get the correct bit count. For longer integration periods, the results of multiple read cycles
have to be accumulated in software.
1.4 Generating Errors
Through Control Register 2, the user can intentionally inject a particular error rate into the transmitted
data stream. Injecting errors allows users to stress communication links and to check the functionality of
error monitoring equipment along the path.
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