參數(shù)資料
型號: DS21552L
廠商: Maxim Integrated Products
文件頁數(shù): 57/137頁
文件大?。?/td> 0K
描述: IC TXRX T1 1-CHIP 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC,J1,T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補(bǔ)償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
DS21352/DS21552
26 of 137
5. PARALLEL PORT
The SCT is controlled via either a non–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an
external microcontroller or microprocessor. The SCT can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.
Electrical Characteristics in Section 24 for more details.
5.1 REGISTER MAP
Table 5-1 REGISTER MAP SORTED BY ADDRESS
ADDRESS
R/W
REGISTER NAME
REGISTER
ABBREVIATION
00
R/W
HDLC Control
HCR
01
R/W
HDLC Status
HSR
02
R/W
HDLC Interrupt Mask
HIMR
03
R/W
Receive HDLC Information
RHIR
04
R/W
Receive Bit Oriented Code
RBOC
05
R
Receive HDLC FIFO
RHFR
06
R/W
Transmit HDLC Information
THIR
07
R/W
Transmit Bit Oriented Code
TBOC
08
W
Transmit HDLC FIFO
THFR
09
R/W
Test 2 SEE NOTE 1
TEST2 (set to 00h)
0A
R/W
Common Control 7
CCR7
0B
not present
0C
not present
0D
not present
0E
not present
0F
R
Device ID
IDR
10
R/W
Receive Information 3
RIR3
11
R/W
Common Control 4
CCR4
12
R/W
In–Band Code Control
IBCC
13
R/W
Transmit Code Definition
TCD
14
R/W
Receive Up Code Definition
RUPCD
15
R/W
Receive Down Code Definition
RDNCD
16
R/W
Transmit Channel Control 1
TCC1
17
R/W
Transmit Channel Control 2
TCC2
18
R/W
Transmit Channel Control 3
TCC3
19
R/W
Common Control 5
CCR5
1A
R
Transmit DS0 Monitor
TDS0M
1B
R/W
Receive Channel Control 1
RCC1
1C
R/W
Receive Channel Control 2
RCC2
1D
R/W
Receive Channel Control 3
RCC3
1E
R/W
Common Control 6
CCR6
1F
R
Receive DS0 Monitor
RDS0M
20
R/W
Status 1
SR1
Table 5-1 REGISTER MAP SORTED BY ADDRESS (Cont.)
ADDRESS
R/W
REGISTER NAME
REGISTER
ABBREVIATION
21
R/W
Status 2
SR2
22
R/W
Receive Information 1
RIR1
23
R
Line Code Violation Count 1
LCVCR1
24
R
Line Code Violation Count 2
LCVCR2
25
R
Path Code Violation Count 1 SEE NOTE 3
PCVCR1
26
R
Path Code violation Count 2
PCVCR2
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