參數(shù)資料
型號: DS21552L
廠商: Maxim Integrated Products
文件頁數(shù): 107/137頁
文件大?。?/td> 0K
描述: IC TXRX T1 1-CHIP 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC,J1,T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補(bǔ)償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
DS21352/DS21552
71 of 137
RPE
HSR.6
Receive Packet End. Set when the HDLC controller detects either the finish of a valid
message (i.e., CRC check complete) or when the controller has experienced a message
fault such as a CRC checking error, or an overrun condition, or an abort has been seen.
The setting of this bit prompts the user to read the RPRM register for details.
RPS
HSR.5
Receive Packet Start. Set when the HDLC controller detects an opening byte. The
setting of this bit prompts the user to read the RPRM register for details.
RHALF
HSR.4
Receive FIFO Half Full. Set when the receive 64–byte FIFO fills beyond the half way
point. The setting of this bit prompts the user to read the RPRM register for details.
RNE
HSR.3
Receive FIFO Not Empty. Set when the receive 64–byte FIFO has at least one byte
available for a read. The setting of this bit prompts the user to read the RPRM register
for details.
THALF
HSR.2
Transmit FIFO Half Empty. Set when the transmit 64–byte FIFO empties beyond the
half way point. The setting of this bit prompts the user to read the TPRM register for
details.
TNF
HSR.1
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO has at least one byte
available. The setting of this bit prompts the user to read the TPRM register for details.
TMEND
HSR.0
Transmit Message End. Set when the transmit HDLC controller has finished sending a
message. The setting of this bit prompts the user to read the TPRM register for details.
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
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