參數(shù)資料
型號： DS21552G
廠商： Maxim Integrated Products
文件頁數(shù)： 98/137頁
文件大?。?/td> 0K
描述： IC TXRX T1 1-CHIP 5V 100-BGA
標(biāo)準(zhǔn)包裝： 1
功能： 單芯片收發(fā)器
接口： E1，HDLC，J1，T1
電路數(shù)： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
包括： DSX-1 和 CSU 線路補償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測器
DS21352/DS21552
63 of 137
RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER
(ADDRESS=1B TO 1D Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCC1 (1B)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCC2 (1C)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCC3 (1D)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
RCC3.7
Receive Channel 24 Code Insertion Control Bit
0 = do not insert data from the RC24 register into the receive data stream
1 = insert data from the RC24 register into the receive data stream
CH1
RCC1.0
Receive Channel 1 Code Insertion Control Bit
0 = do not insert data from the RC1 register into the receive data stream
1 = insert data from the RC1 register into the receive data stream
12. PER–CHANNEL LOOPBACK
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR4.0) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC.
13. CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers
(TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user
programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block
clocks to a UART or LAPD controller in Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a one,
the RCHBLK and TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section 21
for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCBR1 (6C)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCBR2 (6D)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCBR3 (6E)
SYMBOLS
POSITIONS
NAME AND DESCRIPTION
CH1-24
RCBR1.0-3.7
Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TCBR1 (32)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TCBR2 (33)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TCBR3 (34)
SYMBOLS
POSITIONS
NAME AND DESCRIPTION
CH1-24
TCBR1.0-3.7
Transmit Channel Blocking Control Bits.
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DS21552L IC TXRX T1 1-CHIP 5V 100-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21552GN 功能描述:IC TXRX T1 1-CHIP 5V 100-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
DS21552L 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21552L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21552LB 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS21552LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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