參數(shù)資料
型號： DS21552G
廠商： Maxim Integrated Products
文件頁數(shù)： 71/137頁
文件大?。?/td> 0K
描述： IC TXRX T1 1-CHIP 5V 100-BGA
標準包裝： 1
功能： 單芯片收發(fā)器
接口： E1，HDLC，J1，T1
電路數(shù)： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
包括： DSX-1 和 CSU 線路補償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測器
DS21352/DS21552
39 of 137
CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB)
(LSB)
RSRE
RPCSI
RFSA1
RFE
RFF
THSE
TPCSI
TIRFS
SYMBOL
POSITION
NAME AND DESCRIPTION
RSRE
CCR4.7
Receive Side Signaling Re–Insertion Enable. See Section 10.2 for details.
0 = do not re–insert signaling bits into the data stream presented at the RSER pin
1 = reinsert the signaling bits into data stream presented at the RSER pin
RPCSI
CCR4.6
Receive Per–Channel Signaling Insert. See Section 10.2 for more details.
0 = do not use RCHBLK to determine which channels should have signaling re–inserted
1 = use RCHBLK to determine which channels should have signaling re–inserted
RFSA1
CCR4.5
Receive Force Signaling All Ones. See Section 10.2 for more details.
0 = do not force extracted robbed–bit signaling bit positions to a one
1 = force extracted robbed–bit signaling bit positions to a one
RFE
CCR4.4
Receive Freeze Enable. See Section 10.2 for details.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and RSER if CCR4.7 = 1).
RFF
CCR4.3
Receive Force Freeze. Freezes receive side signaling at RSIG (and RSER if
CCR4.7=1); will override Receive Freeze Enable (RFE). See Section 10.2 for details.
0 = do not force a freeze event
1 = force a freeze event
THSE
CCR4.2
Transmit Hardware Signaling Insertion Enable. See Section 10.2 for details.
0 = do not insert signaling from the TSIG pin into the data stream presented at the
TSER pin
1 = insert signaling from the TSIG pin into data stream presented at the TSER pin
TPCSI
CCR4.1
Transmit Per–Channel Signaling Insert. See Section 10.2 for details.
0 = do not use TCHBLK to determine which channels should have signaling inserted
from TSIG
1 = use TCHBLK to determine which channels should have signaling inserted from
TSIG
TIRFS
CCR4.0
Transmit Idle Registers (TIR) Function Select. See Section 2.1 for timing details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER (i.e., Per-Channel
Loopback function)
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DS21552L IC TXRX T1 1-CHIP 5V 100-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21552GN 功能描述:IC TXRX T1 1-CHIP 5V 100-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:*
DS21552L 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21552L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21552LB 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS21552LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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