參數(shù)資料
型號： DS21552G
廠商： Maxim Integrated Products
文件頁數(shù)： 137/137頁
文件大?。?/td> 0K
描述： IC TXRX T1 1-CHIP 5V 100-BGA
標(biāo)準(zhǔn)包裝： 1
功能： 單芯片收發(fā)器
接口： E1，HDLC，J1，T1
電路數(shù)： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
包括： DSX-1 和 CSU 線路補(bǔ)償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測器
DS21352/DS21552
99 of 137
19.2 TAP CONTROLLER STATE MACHINE
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK. See Figure 19-1.
TEST-LOGIC-RESET
Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will
contain the IDCODE instruction. All system logic of the device will operate normally.
RUN-TEST-IDLE
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and
test registers will remain idle.
SELECT-DR-SCAN
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge
on JTCLK moves the controller to the Select-IR-Scan state.
CAPTURE-DR
Data may be parallel-loaded into the test data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test
register will remain at its current value. On the rising edge of JTCLK, the controller will go to the Shift-
DR state if JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH.
SHIFT-DR
The test data register selected by the current instruction will be connected between JTDI and JTDO and
will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected
by the current instruction is not placed in the serial path, it will maintain its previous state.
EXIT1-DR
While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which
terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put
the controller in the Pause-DR state.
PAUSE-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction will retain their previous state. The controller will remain in this state while JTMS is LOW.
A rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2-DR state.
EXIT2-DR
A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR
state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-
DR state.
UPDATE-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of
the test registers into the data output latches. This prevents changes at the parallel output due to changes
in the shift register.
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DS21552L IC TXRX T1 1-CHIP 5V 100-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21552GN 功能描述:IC TXRX T1 1-CHIP 5V 100-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
DS21552L 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21552L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21552LB 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS21552LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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