參數(shù)資料
型號: DS2151Q
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 45/47頁
文件大?。?/td> 413K
代理商: DS2151Q
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
7
Maxim Integrated
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (GPIO1, GPIO2, SCLK, DI, CKSEL, CKIO,
CS)
Input High Threshold Voltage
VIH
0.8 x
VDD
V
Input Low Threshold Voltage
VIL
0.2 x
VDD
V
Input Hysteresis
VIHYS
0.2
V
CKSEL,
CS = VSS
38
-90
Input Leakage Current
IIN
GPIO1, GPIO2, SCLK, DI, CKIO = VDD
38
+90
A
Input Capacitance
CIN
5pF
DIGITAL OUTPUTS (GPIO1, GPIO2, DO, CKIO)
GPIO1, GPIO2, DO
VDD - 0.1
RLOAD =
CKIO (Note 10)
4.9
GPIO1, GPIO2, DO
VDD - 0.15
Output-Voltage High
VOH
RLOAD = 2k
Ω to VSS
CKIO (Note 10)
4.6
V
GPIO1, GPIO2, DO
0.05
RLOAD =
CKIO (Note 10)
0.1
GPIO1, GPIO2, DO
0.2
Output-Voltage Low
VOL
RLOAD = 2k
Ω to VDD
CKIO (Note 10)
0.4
V
FLASH MEMORY
Maximum Erase Cycles
(Notes 11, 12)
10k
Cycles
Minimum Erase Time
tERASE
(Notes 11, 12)
4.2
ms
Minimum Write Time
tWRITE
(Notes 11, 12)
80
s
FLASH Programming Current
IDDFP
Writing to the FLASH or erasing the FLASH
(Note 13)
30
mA
ELECTRICAL CHARACTERISTICS (continued)
(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF = VSS = 0V,
TA = +25°C, unless otherwise noted.) (Note 1)
Note 1:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to VSS.
Note 2:
All modules are off, except internal reference, oscillator, and power-on reset (POR) and CKSEL bit is set to zero.
Note 3:
The CPU and ADC are not on at the same time. The ADC and CPU currents are not additive.
Note 4:
IDACn does not include output buffer currents (IOPLGn or IOPSMn).
Note 5:
For gains above 240, an additional digital gain can be provided by the CPU.
Note 6:
The PWM input data is the 12-bit left-justified data in the 16-bit input field.
Note 7:
PWM gain error measured as:
Note 8:
The internal reference voltage has a nominal value of 5V (4
VBG) even when VDD is greater or less than 5VDC.
Note 9:
Input-referred offset error is the ADC offset error divided by the PGA gain.
Note 10: When the CKIO is configured in output mode to observe the internal oscillator signal, the total current is above the
specified limits.
Note 11: fCLK must be within 5% of 4MHz.
Note 12: Allow a minimum elapsed time of 4.2ms when executing a FLASH erase command, before sending any other command.
Allow a minimum elapsed time of 80s between FLASH write commands.
Note 13: FLASH programming current is guaranteed by design.
GE
PWM
F
Xh
PWM
Xh
PWM
OUT
=
()
()
×
00
100
3584
100%
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參數(shù)描述
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