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參數(shù)資料
| 型號(hào)： | DS21372TN |
| 英文描述： | 3.3V Bit Error Rate Tester BERT |
| 中文描述： | 3.3誤碼率測(cè)試儀誤碼 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 214K |
| 代理商： | DS21372TN |
DS21372
5 of 21
PIN
24
SYMBOL
RL
TYPE
I
DESCRIPTION
Receive Load.
A positive-going edge loads the previous 32 bits of data
received at RDATA into the Pattern Receive Registers. RL is logically
OR’ed with control bit PCR.3. Should be tied to V
SS
if not used.
Receive Data.
Received NRZ serial data, sampled on the rising edge of
RCLK.
Receive Disable.
Set high to prevent the data at RDATA from being
sampled. Set low to allow bits at RDATA to be sampled. Should be tied
to V
SS
if not used. See Figure 6 for timing information. All receive side
operations are disabled when RDIS is high.
Receive Clock.
Input clock from transmission link. 0 to 20 MHz. Can
be a gapped clock. Fully independent from TCLK.
Positive Supply.
3.3 volts.
Signal Ground.
0.0 volts. Should be tied to local ground plane.
Transmit Clock.
Transmit demand clock. 0 to 20 MHz. Can be a
gapped clock. Fully independent of RCLK.
Transmit Disable.
Set high to hold the current bit being transmitted at
TDATA. Set low to allow the next bit to appear at TDATA. Should be
tied to V
SS
if not used. See Figure 7 for timing information. All transmit
side operations are disabled when TDIS is high.
Transmit Data.
Transmit NRZ serial data, updated on the rising edge of
TCLK.
25
RDATA
I
26
RDIS
I
27
RCLK
I
28
29
30
V
DD
V
SS
TCLK
-
-
I
31
TDIS
I
32
TDATA
O
DS21372 REGISTER MAP
Table 2
ADDRESS
R/W
00
R/W
Pattern Set Register 3.
01
R/W
Pattern Set Register 2.
02
R/W
Pattern Set Register 1.
03
R/W
Pattern Set Register 0.
04
R/W
Pattern Length Register.
05
R/W
Polynomial Tap Register.
06
R/W
Pattern Control Register.
07
R/W
Error Insert Register.
08
R
Bit Counter Register 3.
09
R
Bit Counter Register 2.
0A
R
Bit Counter Register 1.
0B
R
Bit Counter Register 0.
REGISTER NAME
ADDRESS
0C
0D
0E
0F
10
11
12
13
14
15
1C
R/W
R
R
R
R
R
R
R
R
R
R/W
R/W
REGISTER NAME
Bit Error Counter Register 3.
Bit Error Counter Register 2.
Bit Error Counter Register 1.
Bit Error Counter Register 0.
Pattern Receive Register 3.
Pattern Receive Register 2.
Pattern Receive Register 1.
Pattern Receive Register 0.
Status Register.
Interrupt Mask Register.
Test Register (see note 1)
NOTE:
1.
The Test Register must be set to 00 hex to insure proper operation of the DS21372.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21372TN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS214 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| DS2141A | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Controller w/Elastic Store RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2141AN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Controller w/Elastic Store RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2141AQ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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