參數(shù)資料
型號: DS21372TN
英文描述: 3.3V Bit Error Rate Tester BERT
中文描述: 3.3誤碼率測試儀誤碼
文件頁數(shù): 12/21頁
文件大?。?/td> 214K
代理商: DS21372TN
DS21372
12 of 21
BIT COUNT REGISTERS
(MSB)
BC31
BC30
BC29
BC28
BC23
BC22
BC21
BC20
BC15
BC14
BC13
BC12
BC7
BC6
BC5
BC4
(LSB)
BC24
BC16
BC8
BC0
BC27
BC19
BC11
BC3
BC26
BC18
BC10
BC2
BC25
BC17
BC9
BC1
BCR3 (addr.=08 Hex)
BCR2 (addr.=09 Hex)
BCR1 (addr.=0A Hex)
BCR0 (addr.=0B Hex)
9.
The Bit Error Count Registers (BECR3 to BECR0) comprise a 32-bit count of bits received in error at
RDATA. The bit error counter is disabled during loss of SYNC. BEC31 is the MSB of the 32-bit count.
The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition,
the user must clear the BECR by either toggling the LC bit or pin. The DS21372 latches the bit error
count into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC
input pin toggles from low to high. The bit count (available via the BCRs) and bit error count are used by
an external processor to compute the BER performance on a loop or channel basis.
BIT ERROR COUNT REGISTERS
BIT ERROR COUNT REGISTERS
(MSB)
BEC31
BEC30
BEC29
BEC28
BEC23
BEC22
BEC21
BEC20
BEC15
BEC14
BEC13
BEC12
BEC7
BEC6
BEC5
BEC4
(LSB)
BEC24
BEC16
BEC8
BEC0
BEC27
BEC19
BEC11
BEC3
BEC26
BEC18
BEC10
BEC2
BEC25
BEC17
BEC9
BEC1
BECR3 (addr.=0C Hex)
BECR2 (addr.=0D Hex)
BECR1 (addr.=0E Hex)
BECR0 (addr.=0F Hex)
10. PATTERN RECEIVE REGISTERS
The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The
operation of these registers depends on the synchronization status of the DS21372. Asserting the RL bit
(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received
at RDATA into the PRR registers. When the DS21372 is in sync (SR.0 = 1) asserting RL will latch the
pattern that to which the device has established synchronization. Since the receiver has no knowledge of
the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an
example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,
11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the
PRR registers.
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