- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379182 > DS21372TN 3.3V Bit Error Rate Tester BERT PDF資料下載
參數(shù)資料
| 型號(hào)： | DS21372TN |
| 英文描述： | 3.3V Bit Error Rate Tester BERT |
| 中文描述： | 3.3誤碼率測試儀誤碼 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 214K |
| 代理商： | DS21372TN |
DS21372
13 of 21
PATTERN RECEIVE REGISTERS
(MSB)
PR31
PR30
PR29
PR23
PR22
PR21
PR15
PR14
PR13
PR7
PR6
(LSB)
PR26
PR25
PR18
PR17
PR10
PR9
PR2
PR1
PR28
PR20
PR12
PR4
PR27
PR19
PR11
PR3
PR24
PR16
PR8
PR0
PRR3 (addr.=10 Hex)
PRR2 (addr.=11 Hex)
PRR1 (addr.=12 Hex)
PRR0 (addr.=13 Hex)
PR5
11. STATUS REGISTER AND INTERRUPT MASK REGISTER
The Status Register (SR) contains information on the current real time status of the DS21372. When a
particular event has occurred, the appropriate bit in the register will be set to a 1. All of the bits in these
registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a
bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. For the BED, BCOF,
and BECOF status bits, they will be cleared when read and will not be set again until the event has
occurred again. For RLOS, RA0, and RA1 status bits, they will be cleared when read if the condition no
longer persists.
The SR register has the unique ability to initiate a hardware interrupt via the
INT
pin. Each of the alarms
and events in the SR can be either masked or unmasked from the interrupt pins via the Interrupt Mask
Register (IMR).
SR: STATUS REGISTER
(ADDRESS=14 HEX)
(MSB) (LSB)
-
RA1
RA0
RLOS
BED
BCOF
BECOF
SYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
-
SR.7
Not Assigned.
Could be any value when read.
RA1
SR.6
Receive All Ones.
Set when 32 consecutive 1s are received;
allowed to be cleared when a 0 is received.
RA0
SR.5
Receive All Zeros.
Set when 32 consecutive 0s are received;
allowed to be cleared when a 1 is received.
RLOS
SR.4
Receive Loss Of Sync.
Set when the device is searching for
synchronization. Once sync is achieved, will remain set until
read.
BED
SR.3
Bit Error Detection.
Set when bit errors are detected.
BCOF
BECOF
SR.2
SR.1
Bit Counter Overflow.
Set when the 32-bit BCR overflows.
Bit Error Count Overflow.
Set when the 32-bit BECR
overflows.
SYNC
SR.0
Sync.
Real time status of the synchronizer (this bit is not
latched). Will be set when synchronization is declared. Will be
cleared when 6 or more bits out of 64 are received in error (if
PCR.2 = 0).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2141A | T1 Controller |
| DS2143 | E1/ISDN-PRI framing transceiver |
| DS2143Q | E1/ISDN-PRI framing transceiver |
| DS21455 | Quad T1/E1/J1 Transceivers |
| DS21455N | Quad T1/E1/J1 Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21372TN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS214 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| DS2141A | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Controller w/Elastic Store RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2141AN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Controller w/Elastic Store RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2141AQ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。