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| 型號(hào)： | DS21352LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 103/137頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX T1 1-CHIP 3.3V 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | HDLC，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 包括： | DSX-1 和 CSU 線路補(bǔ)償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測(cè)器 |
| 產(chǎn)品目錄頁(yè)面： | 1429 (CN2011-ZH PDF) |
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DS21352/DS21552
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Table 15-2 HDLC/BOC CONTROLLER REGISTERS
NAME
FUNCTION
HDLC Control Register (HCR)
general control over the HDLC and BOC controllers
HDLC Status Register (HSR)
key status information for both transmit and receive directions
HDLC Interrupt Mask Register (HIMR)
allows/stops status bits to/from causing an interrupt
Receive HDLC Register (RHIR)
status information on receive HDLC controller
Receive BOC Register (RBOC)
status information on receive BOC controller
Receive HDLC FIFO Register (RHFR)
access to 64–byte HDLC FIFO in receive direction
Receive HDLC DS0 Control Register 1 (RDC1)
controls the HDLC function when used on DS0 channels
Receive HDLC DS0 Control Register 2 (RDC2)
controls the HDLC function when used on DS0 channels
Transmit HDLC Register (THIR)
status information on transmit HDLC controller
Transmit BOC Register (TBOC)
enables/disables transmission of BOC codes
Transmit HDLC FIFO Register (THFR)
access to 64–byte HDLC FIFO in transmit direction
Transmit HDLC DS0 Control Register 1 (TDC1)
controls the HDLC function when used on DS0 channels
Transmit HDLC DS0 Control Register 2 (TDC2)
controls the HDLC function when used on DS0 channels
15.3.2 STATUS REGISTER FOR THE HDLC
Four of the HDLC/BOC controller registers (HSR, RHIR, RBOC, and THIR) provide status information.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. Some of the bits in these four HDLC status registers are latched and some are real
time bits that are not latched. Section 15.3.2 contains register descriptions that list which bits are latched
and which are not. With the latched bits, when an event occurs and a bit is set to a one, it will remain set
until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the
event has occurred again. The real time bits report the current instantaneous conditions that are occurring
and the history of these bits is not latched.
Like the other status registers, the user will always proceed a read of any of the four registers with a
write. The byte written to the register will inform the device which of the latched bits the user wishes to
read and have cleared (the real time bits are not affected by writing to the status register). The user will
write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in
the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit
location, the read register will be updated with current value and it will be cleared. When a zero is written
to a bit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write–read–write (for polled driven access) or write–read (for interrupt driven
access) scheme allows an external microcontroller or microprocessor to individually poll certain bits
without disturbing the other bits in the register. This operation is key in controlling the device with
higher–order software languages.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21352LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21354 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3.3V/5V E1 Single-Chip Transceivers |
| DS21354DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS21354 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS21354G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21354GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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