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| 型號(hào)： | DS21352L |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 100/137頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX T1 1-CHIP 3.3V 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | HDLC，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 包括： | DSX-1 和 CSU 線路補(bǔ)償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測(cè)器 |
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DS21352/DS21552
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14.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz (CCR1.4=1) clock can be applied
to the TSYSCLK input. If the user selects to apply a 2.048 MHz clock to the TSYSCLK pin, then the data
input at TSER will be ignored every fourth channel. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29
(timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. The user must supply an 8 kHz frame sync
pulse to the TSSYNC input. Also, in 2.048 MHz applications, the TCHBLK output will be forced high
during the channels ignored by the framer. See Section 21 for more details. Controlled slips in the
transmit elastic store are reported in the RIR2.3 bit and the direction of the slip is reported in the RIR2.5
and RIR2.4 bits.
14.3 ELASTIC STORES INITIALIZATION
There are two elastic store initializations that may be used to improve performance in certain
applications, Elastic Store Reset and Elastic Store Align. Both of these involve the manipulation of the
elastic store’s read and write pointers and are useful primarily in synchronous applications (RSYSCLK /
TSYSCLK are locked to RCLK / TCLK respectively). See table below for details.
Table 14-1 ELASTIC STORE DELAY AFTER INITIALIZATION
Initialization
Register. Bit
Delay
Receive Elastic Store Reset
Transmit Elastic Store Reset
CCR7.5
CCR7.4
8 Clocks < Delay < 1 Frame
1 Frame < Delay < 2 Frames
Receive Elastic Store Align
Transmit Elastic Store Align
CCR6.6
CCR6.5
Frame < Delay < 1 Frames
14.4 MINIMUM DELAY MODE
Elastic store minimum delay mode may be used when the elastic store’s system clock is locked to its
network clock (i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for
the transmit side). CCR3.7 and CCR3.0 enable the transmit and receive elastic store minimum delay
modes. When enabled the elastic stores will be forced to a maximum depth of 32 bits instead of the
normal 386 bits. This feature is useful primarily in applications that interface to a 2.048MHz bus.
Certain restrictions apply when minimum delay mode is used. In addition to the restriction mentioned
above, RSYNC must be configured as an output when the receive elastic store is in minimum delay mode
and TSYNC must be configured as an output when transmit minimum delay mode is enabled. In a
typical application RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is
connected to TSSYNC (frame input mode). All of the slip contention logic in the framer is disabled
(since slips cannot occur). On power–up after the RSYSCLK and TSYSCLK signals have locked to their
respective network clock signals, the elastic store reset bits (CCR7.4 and CCR7.5) should be toggled
from a zero to a one to insure proper operation.
Table 14-2 MINIMUM DELAY MODE CONFIGURATION
Hardware Requirements
Register Settings
Transmit
TSYSCLK can be 1.544MHz or 2.048MHz and must
be locked to TCLK (1.544MHz). TSYNC is an output
CCR3.0 = 1, CCR1.7 = 1
TCR2.2 = 1
Receive
RSYSCLK can be 1.544MHz or 2.048MHz and must
be locked to RCLK (1.544MHz). RSYNC is an output.
CCR3.7 = 1, CCR1.2 = 1
RCR2.3 = 0
15. HDLC CONTROLLER
This device has an enhanced HDLC controller configurable for use with the Facilities Data Link or DS0s.
There are 64 byte buffers in the transmit and receive paths. The user can select any DS0 or multiple
DS0s as well as any specific bits within the DS0(s) to pass through the HDLC controller. Note that
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21352L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21352LB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21352LB+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21352LBN | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21352L-C02 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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