參數(shù)資料
型號: DS21352L+
廠商: Maxim Integrated Products
文件頁數(shù): 101/137頁
文件大小: 0K
描述: IC TXRX T1 1-CHIP 3.3V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
功能: 單芯片收發(fā)器
接口: HDLC,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS21352/DS21552
66 of 137
TBOC.6 = 1 and TDC1.7 = 1 cannot exist without corrupting the data in the FDL. See Table 15-1 for
configuring the transmit HDLC controller.
Table 15-1 TRANSMIT HDLC CONFIGURATION
Function
TBOC.6
TDC1.7
TCR1.2
DS0(s)
0
1
1 or 0
FDL
1
0
1
Disable
0
1 or 0
Note that the BOC controller is functional when the HDLC controller is used for DS0s. Section 15.3 contains all of the HDLC
and BOC registers and information on FDL/Fs Extraction and Insertion with and without the HDLC controller.
15.1 HDLC FORr DS0s
When using the HDLC controllers for DS0s, the same registers shown in section 15.3.2 will be used
except for the TBOC and RBOC registers and bits HDLC.7, HSR.7, and HIMR.7. As a basic guideline
for interpreting and sending HDLC messages and BOC messages, the following sequences can be
applied.
15.1.1 RECEIVE AN HDLC MESSAGE
1. Enable RPS interrupts.
2. Wait for interrupt to occur.
3. Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt.
4. Read RHIR to obtain REMPTY status.
a. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO.
a1. If CBYTE=0 then skip to step 5.
a2. If CBYTE=1 then skip to step 7.
b. If REMPTY=1, then skip to step 6.
5. Repeat step 4.
6. Wait for interrupt, skip to step 4.
7. If POK=0, then discard whole packet, if POK=1, accept the packet.
8. Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
15.1.2 TRANSMIT AN HDLC MESSAGE
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO
is empty by reading the TEMPTY status bit in the THIR register.
2. Enable either the THALF or TNF interrupt.
3. Read THIR to obtain TFULL status.
a. If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when the last byte is to be
written, in this case set TEOM=1 before writing the byte and then skip to step 6).
b. If TFULL=1, then skip to step 5.
4. Repeat step 3.
5. Wait for interrupt, skip to step 3.
6. Disable THALF or TNF interrupt and enable TMEND interrupt.
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
15.2 FDL/Fs EXTRACTION AND INSERTION
The device has the ability to extract/insert data from/ into the Facility Data Link (FDL) in the ESF
framing mode and from/into Fs–bit position in the D4 framing mode. Since SLC–96 utilizes the Fs–bit
position, this capability can also be used in SLC–96 applications. The device contains a complete HDLC
and BOC controller which can be used for the FDL or for DS0s. Using the HDLC controller for the FDL
is covered in Section 15.3.3. To allow for backward compatibility with earlier devices, legacy
functionality is maintained for the FDL, which is covered in Section 15.4. Section 15.5 covers D4 and
SLC–96 operation.
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