參數(shù)資料
型號: DS21352L+
廠商: Maxim Integrated Products
文件頁數(shù): 1/137頁
文件大?。?/td> 0K
描述: IC TXRX T1 1-CHIP 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: HDLC,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補(bǔ)償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
1 of 137
120501
FEATURES
§
Complete DS1/ISDN–PRI/J1 transceiver functionality
§
Long and Short haul LIU
§
Crystal–less jitter attenuator
§
Generates DSX–1 and CSU line build-outs
§
HDLC controller with 64-byte buffers Configurable for
FDL or DS0 operation
§
Dual two–frame elastic store slip buffers that can
connect to asynchronous backplanes up to 8.192MHz
§
8.192MHz clock output locked to RCLK
§
Interleaving PCM Bus Operation
§
Per-channel loopback and idle code insertion
§
8-bit parallel control port muxed or nonmuxed buses
(Intel or Motorola)
§
Programmable output clocks for Fractional T1
§
Fully independent transmit and receive functionality
§
Generates/detects in-band loop codes from 1 to 8 bits
in length including CSU loop codes
§
IEEE 1149.1 JTAG-Boundary Scan
§
Pin compatible with DS2152/54/354/554 SCTs
§
100-pin LQFP package (14 mm x 14 mm) 3.3V
(DS21352) or 5V (DS21552) supply; low power
CMOS
ORDERING INFORMATION
DS21352L
(0
°C to +70°C)
DS21352LN
(-40
°C to +85°C)
DS21552L
(0
°C to +70°C)
DS21552LN
(-40
°C to +85°C)
DESCRIPTION
The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1
lines whether they are DS1 long haul or DSX–1 short haul. The clock recovery circuitry automatically
adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX–1 line build
outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator
(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The
framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also
used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of
internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12–90),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
1
100
PIN ASSIGNMENT
3.3V DS21352 and 5V DS21552
T1 Single-Chip Transceivers
www.maxim-ic.com
DS21352
DS21552
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