
DS1962/DS1963
020698 7/22
ADDRESS REGISTERS
Figure 6
TARGET ADDRESS (TA1)
TARGET ADDRESS (TA2)
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
T7
T6
T5
T4
T3
T2
T1
T0
T15
T14
T13
T12
T11
T10
T9
T8
AA
1)
PF
E4
E3
E2
E1
E0
1) THIS BIT WILL ALWAYS BE 0.
Read Memory [F0H]
The read memory command may be used to read the
entire memory. After issuing the command, the master
must provide the 2–byte target address. After the two
bytes, the master reads data beginning from the target
address and may continue until the end of memory, at
which point logic 1’s will be read. It is important to realize
that the target address registers will contain the address
provided. The ending offset/data status byte is unaf-
fected.
The hardware of the DS196X provides a means to
accomplish error–free writing to the memory section. To
safeguard reading data in the 1–Wire environment and
to simultaneously speed up data transfers, it is recom-
mended to packetize data into data packets of the size
of one memory page each. Such a packet would typi-
cally store a 16–bit CRC with each page of data to insure
rapid, error–free data transfers that eliminate having to
read a page multiple times to determine if the received
data is correct or not. (See the Book of DS19xx iButton
Standards, Chapter 7 for the recommended file struc-
ture.)
Read Memory + Counter [A5H]
The Read Memory + Counter command is used to read
memory data together with the write cycle counter
associated with the addressed page of data memory.
The additional information is transmitted by the DS196X
as the end of a memory page is encountered. Following
the current value of the page write cycle counter the
DS196X transmits 32 tamper–detect bits and a 16–bit
CRC generated by the DS196X. The tamper–detect
bits are factory–preset to 55555555H and locked. Tam-
pering with the device will change this data pattern.
After having sent the command code of the Read
Memory + Counter command, the bus master sends a
two–byte address (TA1=(T7:T0), TA2=(T15:T8)) that
indicates a starting byte location within the data field.
With the subsequent read data time slots the master
receives data from the DS196X starting at the initial
address and continuing until the end of a 32–byte page
is reached. At that point the bus master will send 80
additional read data time slots and receive the contents
of the 32–bit write cycle counter associated with the
addressed page, the status of the 32 tamper–detect bits
and a 16–bit CRC. With subsequent read data time
slots the master will receive data starting at the begin-
ning of the next page followed again by the contents of
the page write cycle counter, tamper–detect bits and
CRC for that page. This sequence will continue until the
final page and its accompanying data is read by the bus
master. When applying the Read Memory + Counter
command to a page that does not have a page write
cycle counter associated, the the master will read
FFFFFFFFH intead of a valid cycle count.
With the initial pass through the Read Memory +
Counter flow chart the 16–bit CRC value is the result of
shifting the command byte into the cleared CRC gener-
ator, followed by the two address bytes, the contents of
the data memory, the write page cycle counter and the
tamper–detect bits. Subsequent passes through the
Read Memory + Counter flow chart will generate a
16–bit CRC that is the result of clearing the CRC gener-
ator and then shifting in the contents of the data memory
page, its associated page write cycle counter and tam-
per–detect bits. After the 16–bit CRC of the last page is
read, the bus master will receive logical 1’s from the
DS196X until a Reset Pulse is issued. The Read
Memory + Counter command sequence can be ended
at any point by issuing a Reset Pulse.