參數(shù)資料
型號(hào)： DS1962
廠商： Maxim Integrated Products, Inc.
英文描述： 1K-Bit Monetary iButton(1K位貨幣按鈕)
中文描述： 1K位貨幣iButton的（每1000位貨幣按鈕）
文件頁(yè)數(shù)： 13/22頁(yè)
文件大?。?/td> 147K
代理商： DS1962
DS1962/DS1963
020698 13/22
HARDWARE CONFIGURATION
Figure 8
V
PUP
DS196X 1–WIRE PORT
R
X
T
X
100 OHM
MOSFET
5 k
TYP.
R
X
T
X
R
X
=
RECEIVE
T
X
=
TRANSMIT
5
μ
A
TYP.
BUS MASTER
DATA
OPEN DRAIN
PORT PIN
1–WIRE BUS SYSTEM
The 1–Wire bus is a system which has a single bus mas-
ter and one or more slaves. In all instances the DS196X
is a slave device. The bus master is typically a micro-
controller. The discussion of this bus system is broken
down into three topics: hardware configuration, transac-
tion sequence, and 1–Wire signaling (signal types and
timing). A 1–Wire protocol defines bus transactions in
terms of the bus state during specific time slots that are
initiated on the falling edge of sync pulses from the bus
master. For a more detailed protocol description, refer
to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION
The 1–Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive it
at the appropriate time. To facilitate this, each device
attached to the 1–Wire bus must have open drain or
3–state outputs. The 1–Wire port of the DS196X is open
drain with an internal circuit equivalent to that shown in
Figure 8. A multidrop bus consists of a 1–Wire bus with
multiple slaves attached. At regular speed the 1–Wire
bus has a maximum data rate of 16.3k bits per second.
The speed can be boosted to 142k bits per second by
activating the Overdrive Mode. The 1–Wire bus
requires a pull–up resistor of approximately 5 k
.
The idle state for the 1–Wire bus is high. If for any rea-
son a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to
resume. If this does not occur and the bus is left low for
more than 16
μ
s (Overdrive Speed) or more than 120
μ
s
(regular speed), one or more devices on the bus may be
reset.
TRANSACTION SEQUENCE
The protocol for accessing the DS196X via the 1–Wire
port is as follows:
Initialization
ROM Function Command
Memory Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1–Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by presence pulse(s) transmitted by the slave(s).
The presence pulse lets the bus master know that the
DS196X is on the bus and is ready to operate. For more
details, see the “1–Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can
issue one of the six ROM function commands. All ROM
function commands are eight bits long. A list of these
commands follows (refer to flowchart in Figure 9):
Read ROM [33H]
This command allows the bus master to read the
DS196X’s 8–bit family code, unique 48–bit serial num-
ber, and 8–bit CRC. This command can only be used if
there is a single DS196X on the bus. If more than one
slave is present on the bus, a data collision will occur
when all slaves try to transmit at the same time (open
drain will produce a wired–AND result). The resultant
family code and 48–bit serial number will result in a mis-
match of the CRC.
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