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參數(shù)資料
| 型號： | DS1844 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digital Potentiometer(四路數(shù)字電位器) |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 95K |
| 代理商： | DS1844 |
DS1844
042498 3/12
While RST is high and R/W is low, (the write or load
state) the cascade data output, D
OUT
will be inhibited;
preventing the passing of data from D
IN
to D
OUT
. How-
ever, when RST is low data is passed directly from D
IN
to D
OUT
.
When reading data, the R/W input should be in a high
state. Once RST has enabled the port, data can be
clocked out of the device, and will appear on the D
OUT
terminal. A data bit will be valid on the falling edge of a
clock pulse, after a maximum time period of 20 ns (of
that falling edge). Data will appear on D
OUT
, most sig-
nificant bit (MSB) first and starting with potentiome-
ter–0; followed by potentiometer–1 and so forth.
2–Wire Addressable Serial Port Control
The 2–wire serial port interface supports a bi–direc-
tional data transmission protocol with device addres-
sing. A device that sends data on the bus is defined as a
transmitter, and a device receiving data as a receiver.
The device that controls the message is called a “mas-
ter”. The devices that are controlled by the master are
“slaves”. The bus must be controlled by a master device
which generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions. The DS1844 operates as a slave on the two–wire
bus. Connections to the bus are made via the open–
drain I/O lines SDA and SCL. The 2–wire serial port is
selected when the port select input, PS, is in a high–
state. The following I/O terminals control the 2–wire
serial port: SDA, SCL, A0, A1, A2, PS=1. Timing dia-
grams for the 2–wire serial port can be found in Figures
4 through 8. Timing information for the 2–wire serial port
is provided in the AC Electrical Characteristics table for
2–wire serial communications.
The following bus protocol has been defined (See Fig-
ure 4).
Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be inter-
preted as control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy:
Both data and clock lines remain HIGH.
Start data transfer:
A change in the state of the data
line, from HIGH to LOW, while the clock is HIGH, defines
a START condition.
Stop data transfer:
A change in the state of the data
line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data valid:
The state of the data line represents valid
data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock
signal. The data on the line can be changed during the
LOW period of the clock signal. There is one clock pulse
per bit of data. Figure 4 details how data transfer is
accomplished on the two–wire bus. Depending upon
the state of the R/W bit, two types of data transfer are
possible.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP
conditions is not limited, and is determined by the mas-
ter device. The information is transferred byte–wise and
each receiver acknowledges with a ninth bit.
Within the bus specifications a regular mode (100 KHz
clock rate) and a fast mode (400 KHz clock rate) are
defined. The DS1844 works in both modes.
Acknowledge:
Each receiving device, when
addressed, is obliged to generate an acknowledge after
the reception of each byte. The master device must
generate an extra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
1. Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the command/control byte. Next follows a number
of data bytes. The slave returns an acknowledge bit
after each received byte.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1844_05 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Quad Digital Potentiometer |
| DS1844-010 | 功能描述:數(shù)字電位計 IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1844-010+ | 功能描述:數(shù)字電位計 IC Quad RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1844-050 | 功能描述:數(shù)字電位計 IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1844-050+ | 功能描述:數(shù)字電位計 IC Quad RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
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